Liquid crystal display device and image display device

ABSTRACT

A liquid crystal display device includes at least a common electrode line, a common electrode and a pixel electrode in each pixels, the common electrode line comprising a first common electrode line which extends in the extending direction of the gate lines and a second common electrode line which extends in the extending direction of the drain lines in the pixel region, the first common electrode line and the second common electrode line are spaced apart from each other by way of a first insulating film, the first common electrode line and the second common electrode line are connected via an opening portion formed in the first insulating film, and a second insulating film is formed over the opening portion.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a image display debice andliquid crystal display device, and more particularly to an active matrixliquid crystal display device of a thin film transistor (hereinafterreferred to as “TFT”) type or the like and a manufacturing methodthereof.

[0003] 2. Description of the Related Art

[0004] An IPS mode liquid crystal display device has been known foradopting a method for realizing a wide viewing angle in JapaneseLaid-open Patent Publication 36058/1995 and the like. Further, a methodwhich arranges pixel electrodes and a common electrode on an organicresin via through holes formed in the resin has been proposed inJapanese Laid-open Patent Publication 230378/1997. Further, as activeelements which perform switching, thin film transistors (hereinafterreferred to as TFTs) using polysilicon have been known other than TFTsusing amorphous silicon.

SUMMARY OF INVENTION

[0005] The IPS type liquid crystal display device has a drawback thatthe numerical aperture is lower than that of a TN type liquid crystaldisplay device and hence, the improvement of the numerical aperture hasbeen a task of the IPS type liquid crystal display device heretofore.Further, to cope with a demand for video digital media including alarge-sized liquid crystal television set, there has been a task thatthe high luminance must be realized and a further uniform display mustbe realized by reducing the influence of wiring delay in a liquidcrystal display device having a large-sized screen.

[0006] Further, when a screen size of the liquid crystal display deviceadopting the IPS display method is large-sized and the resolutionrequires the high definition, there arises a drawback that the luminanceirregularities, the smear or the like is worsened and hence, the imagequality is degraded. In the IPS type display device using an activematrix type driving, liquid crystal is driven by a lateral electricfield applied between a pixel electrode and a common electrode of eachpixel. Since the pixel electrode is independently driven at every pixel,the delay time of each pixel is determined based on a driving abilitywith respect to a sum of the liquid crystal capacitance of the pixel TFTand the holding capacitance. In the IPS type display device, a value ofthe liquid crystal capacitance is small and a value of the holdingcapacitance is large compared to those of the TN type display device. Onthe other hand, the common electrode is formed of lines connected in thescreen and wiring delay with respect to the resistivity of the electrodematerial and a load of the capacitance value with other lines causes adelay time which deteriorates the image quality. To review each pixel,the holding capacitance is the largest factor which causes the wiringdelay. Accordingly, inventors of the present invention have found thatthe necessity to decrease the wiring delay time of the common electrodeis particularly effective to enhance the image quality.

[0007] Further, the inventors have also found that to reduce the numberof driving ICs arranged outside by incorporating a circuit for drivingdrain lines into a TFT substrate made of glass or the like, it isnecessary to decrease the wiring delay of the drain lines. Accordingly,the liquid crystal display device has to cope with a task that the drainline capacitance must be reduced.

[0008] It is one advantage of the present invention to realize an IPStype liquid crystal display device which can realize the enhancement ofnumerical aperture. It is another advantage of the present invention torealize an IPS type liquid crystal display device which can realize thehigh luminance. It is still another advantage of the present inventionto realize a liquid crystal display device which can reduce theinfluence of wiring delay and can improve the image quality even whenthe liquid crystal display device has a large screen.

[0009] Other advantages of the present invention will become apparentthrough the specification of the present application.

[0010] To describe main constitutional examples of the presentinvention, they are as follows.

[0011] (1)

[0012] In a liquid crystal display device having a liquid crystal layerand a color filter layer sandwiched between a first transparentsubstrate and a second transparent substrate, having a plurality of gatelines, a plurality of drain lines which cross the plurality of gatelines in a matrix array and thin film transistors formed correspondingto respective crossing points of the gate lines and the drain lines onthe first substrate, constituting pixel regions from regions each ofwhich is surrounded by the neighboring gate lines and the neighboringdrain lines, wherein each pixel includes at least a common electrodeline, a common electrode and a pixel electrode,

[0013] the common electrode line comprising a first common electrodeline which extends in the extending direction of the gate lines and asecond common electrode line which extends in the extending direction ofthe drain lines in the pixel region, the first common electrode line andthe second common electrode line are spaced apart from each other by wayof a first insulating film, the first common electrode line and thesecond common electrode line are connected via an opening portion formedin the first insulating film, and a second insulating film is formedover the opening portion.

[0014] (2)

[0015] In the above-mentioned means (1), the first common electrode lineand the second common electrode line include at least the secondinsulating film between the common electrode and the′ first and secondcommon electrode lines in the pixel region, and the common electrodeincludes a portion which is arranged over the drain line by way of atleast the second insulating film such that the portion has a widthlarger than a width of the drain line.

[0016] (3)

[0017] In a liquid crystal display device having a liquid crystal layerand a color filter layer sandwiched between a first transparentsubstrate and a second transparent substrate, having a plurality of gatelines, a plurality of drain lines which cross the plurality of gatelines in a matrix array and thin film transistors formed correspondingto respective crossing points of the gate lines and the drain lines onthe first substrate, constituting pixel regions from regions each ofwhich is surrounded by the neighboring gate lines and the neighboringdrain lines, wherein each pixel includes at least a common electrodeline and a pixel electrode,

[0018] the liquid crystal display device comprising a first island-likeelectrode in the pixel region, an opening portion formed in a firstinsulating film which covers the first island-like electrode, a commonelectrode line which extends in the extending direction of the drainlines, wherein the first island-like electrode and the common electrodeline are connected via the opening portion, the first island-likeelectrode constitutes a lower electrode, and a second island-likeelectrode which is connected to a source of the thin film transistor andis formed on the first insulating film constitutes an upper electrodethus forming holding capacitance.

[0019] (4)

[0020] In the means (3), the liquid crystal display device includes thecommon electrodes which are formed over an insulating film which coversthe drain line over the first substrate, the common electrodes areconnected in a matrix array between neighboring pixels, and the commonelectrodes include portions which have a width wider than a width of thedrain lines over an insulating film which are applied onto the drainlines.

[0021] (5)

[0022] In the means (3), the insulating film of the holding capacitanceis an inorganic insulating film which covers the gate line of the thinfilm transistor.

[0023] (6)

[0024] In the means (3), the first island-like electrode is constitutedof a semiconductor layer of the thin film transistor and the insulatingfilm of the holding capacitance includes at least a gate insulating filmof the thin film transistor.

[0025] (7)

[0026] In a liquid crystal display device having a liquid crystal layerand a color filter layer sandwiched between a first substrate and asecond substrate, having a plurality of gate lines, a plurality of drainlines which cross the plurality of gate lines in a matrix array and thinfilm transistors formed corresponding to respective crossing points ofthe gate lines and the drain lines on the first substrate, constitutingpixel regions from regions each of which is surrounded by theneighboring gate lines and the neighboring drain lines, wherein eachpixel includes at least a common electrode line, a common electrode anda pixel electrode,

[0027] the liquid crystal display device comprising a common electrodeline which extends in the extending direction of the drain line as thecommon electrode line, an island-like metal pixel electrode which isconnected to a source of the thin film transistor, wherein the pixelregion includes an opening portion which is divided into 6 or moreopening portions between the neighboring drain lines, at least 1 dividedopening portion is arranged between the island-like metal pixelelectrode and one of the neighboring drain lines, at least 2 dividedopening portions are arranged between the common electrode line and theother of the neighboring drain lines, and at least 3 divided openingportions are arranged between the island-like metal pixel electrode andthe common electrode line.

[0028] (8)

[0029] In a liquid crystal display device having a liquid crystal layerand a color filter layer sandwiched between a first substrate and asecond substrate, having a plurality of gate lines, a plurality of drainlines which cross the plurality of gate lines in a matrix array and thinfilm transistors formed corresponding to respective crossing points ofthe gate lines and the drain lines on the first substrate, constitutingpixel regions from regions each of which is surrounded by theneighboring gate lines and the neighboring drain lines, wherein eachpixel includes at least a common electrode line, a common electrode anda pixel electrode,

[0030] the liquid crystal display device comprising a common electrodeline which extends in the extending direction of the drain line as thecommon electrode line, an island-like metal pixel electrode which isconnected to a source of the thin film transistor, wherein the pixelregion includes an opening portion which is divided into 8 or moreopening portions between the neighboring drain lines, at least 3 dividedopening portions are arranged between the island-like metal pixelelectrode and one of the neighboring drain lines, at least 2 dividedopening portions are arranged between the common electrode line and theother of the neighboring drain lines, and at least 3 divided openingportions are arranged between the island-like metal pixel electrode andthe common electrode line.

[0031] (9)

[0032] In a liquid crystal display device having a liquid crystal layerand a color filter layer sandwiched between a first substrate and asecond substrate, having a plurality of gate lines, a plurality of drainlines which cross the plurality of gate lines in a matrix array and thinfilm transistors formed corresponding to respective crossing points ofthe gate lines and the drain lines on the first substrate, constitutingpixel regions from regions each of which is surrounded by theneighboring gate lines and the neighboring drain lines, wherein eachpixel includes at least a common electrode line, a transparent commonelectrode and a transparent pixel electrode,

[0033] the transparent common electrode and the transparent pixelelectrode are formed on a same layer above the drain lines, the liquidcrystal display device includes a common electrode line which extends inthe extending direction of the drain line as the common electrode line,a metal pixel electrode which is connected to a source of the thin filmtransistor, wherein the pixel region includes an opening portion whichis divided into 6 or more opening portions between the neighboring drainlines, the metal pixel electrode is arranged below the transparent pixelelectrode which is closest to one drain line of the neighboring drainlines, the common electrode line is arranged close to the other drainline of the neighboring drain lines and below the transparent commonelectrode which is not arranged on the other drain line, and at least 1or more transparent common electrode or 1 or more transparent pixelelectrodes are arranged between the metal pixel electrode and the commonelectrode line.

[0034] (10)

[0035] In a liquid crystal display device having a liquid crystal layerand a color filter layer sandwiched between a first substrate and asecond substrate, having a plurality of gate lines, a plurality of drainlines which cross the plurality of gate lines in a matrix array and thinfilm transistors formed corresponding to respective crossing points ofthe gate lines and the drain lines on the first substrate, constitutingpixel regions from regions each of which is surrounded by theneighboring gate lines and the neighboring drain lines, wherein eachpixel includes at least a common electrode line, a common electrode anda pixel electrode,

[0036] the liquid crystal display device comprising a metal pixelelectrode which is arranged in a region sandwiched by the neighboringdrain lines, a common electrode which extends in the extending directionof the drain line as the common electrode, and a distance between one ofthe neighboring drain lines and the metal pixel electrode, a distancebetween the metal pixel electrode and the common electrode and adistance between the common electrode and the other of the neighboringdrain lines are set to approximately equal with respect to the number ofdivision of the pixel region.

[0037] (11)

[0038] In any one of means (7) to (10), the liquid crystal displaydevice includes a first common electrode line which extends in theextending direction of the gate lines and a second common electrode linewhich extends in the extending direction of the drain line as the commonelectrode line, and the first common electrode line and the secondcommon electrode line are connected to each other via an opening portionof an insulating film in the pixel region.

[0039] (12)

[0040] In the means (10), the approximately equal distances with respectto the number of division of the pixel region are set to 3+3+2 in theliquid crystal display device in which the number of division of theregion between the neighboring drain signal lines is 8, are set to 3+3+4in the liquid crystal display device in which the number of division ofthe region between the neighboring drain signal lines is 10, and are setto 5+4+3 in the liquid crystal display device in which the number ofdivision of the region between the neighboring drain signal lines is 12.

[0041] (13)

[0042] In a liquid crystal display device having a liquid crystal layerand a color filter layer sandwiched between a first transparentsubstrate and a second transparent substrate, having a plurality of gatelines, a plurality of drain lines which cross the plurality of gatelines in a matrix array and thin film transistors formed correspondingto respective crossing points of the gate lines and the drain lines onthe first substrate, constituting pixel regions from regions each ofwhich is surrounded by the neighboring gate lines and the neighboringdrain lines, wherein each pixel includes at least a holding capacitanceline and a pixel electrode,

[0043] the liquid crystal display device comprising a first island-likeelectrode in the pixel region, an opening portion formed in a firstinsulating film which covers the first island-like electrode, a holdingcapacitance line which extends in the extending direction of the drainlines, wherein the first island-like electrode and the holdingcapacitance line are connected via the opening portion, the firstisland-like electrode constitutes a lower electrode, and a second island-like electrode which is connected to a source of the thin filmtransistor and is formed on the first insulating film constitutes anupper electrode thus forming holding capacitance between the first andsecond island-like electrodes.

[0044] (14)

[0045] In the means (13), the liquid crystal display device includes asecond holding capacitance line which extends in the extending directionof the gate lines, and the second holding capacitance line and theholding capacitance line which extends in the extending direction of thedrain lines are electrically connected via a through hole formed in thefirst insulating film.

[0046] (15)

[0047] In the means (13), the liquid crystal display device includes asecond holding capacitance line which extends in the extending directionof the gate lines and the second holding capacitance line also functionsas the first island-like electrode.

[0048] (16)

[0049] In a liquid crystal display device having a liquid crystal layerand a color filter layer sandwiched between a first transparentsubstrate and a second transparent substrate, having a plurality of gatelines, a plurality of drain lines which cross the plurality of gatelines in a matrix array and thin film transistors formed correspondingto respective crossing points of the gate lines and the drain lines onthe first substrate, constituting pixel regions from regions each ofwhich is surrounded by the neighboring gate lines and the neighboringdrain lines, wherein each pixel includes a common electrode line, atransparent common electrode and a pixel electrode,

[0050] an insulating film is formed over the gate line, the transparentcommon electrode is formed over the insulating film and has a regionwhich covers the insulating film and has a width which is larger than awidth of the gate line, and the transparent electrode line having thewidth wider than the width of the gate line plays a role of a blackmatrix in the liquid crystal display device.

[0051] (17)

[0052] In the means (16), the transparent electrode line having thewidth wider than the width of the gate line also covers a semiconductorlayer of the thin film transistor.

[0053] (18)

[0054] In the means (16), the insulating film is an organic insulatingfilm made of acrylic resin or the like.

[0055] (19)

[0056] In any one of the means (1), (2), (4), (7), (8), (9), (10) and(12), the common electrode and the pixel electrodes are formed of atransparent electrode and both electrodes are formed as an uppermostlayer of the first substrate below an orientation film.

[0057] (20)

[0058] In either any one of the means (1) to (10) or any one of themeans (12) to (18), the liquid crystal display device is a lateralelectric field type liquid crystal display device.

[0059] (21)

[0060] In either any one of the means (1) to (10) or any one of themeans (12) to (18), a semiconductor layer of the thin film transistor isformed of polysilicon.

[0061] (22)

[0062] An image display device which is used as a liquid crystaltelevision set is constituted using an active matrix type liquid crystaldisplay device adopting either any one of the means (1) to (10) or anyone of the means (12) to (18).

[0063] (23)

[0064] An image display device which is used as a liquid crystal monitoris constituted using an active matrix type liquid crystal display deviceadopting either any one of the means (1) to (10) or any one of the means(12) to (18).

[0065] (24)

[0066] An image display device which is used as an integral typepersonal computer is constituted using an active matrix type liquidcrystal display device adopting either any one of the means (1) to (10)or any one of the means (12) to (18).

[0067] Further constitutional examples of the present invention will beapparent in the specification of the present application which includesclaims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0068]FIG. 1 is a plan view of an essential part of a pixel of a TFTliquid crystal display device according to one embodiment of the presentinvention.

[0069]FIG. 2 is a cross-sectional view of an essential part of a pixeltaken along a line 2-2′ in FIG. 1.

[0070]FIG. 3 is a cross-sectional view of an essential part of a pixeltaken along a line 3-3′ in FIG. 1.

[0071]FIG. 4 is a cross-sectional view of an essential part of a pixeltaken along a line 4-4′ in FIG. 1.

[0072]FIG. 5 is a cross-sectional view for explaining a manufacturingmethod of a TFT substrate of the TFT liquid crystal display deviceaccording to one embodiment of the present invention up to thecompletion of the first photolithography step.

[0073]FIG. 6 is a cross-sectional view for explaining the manufacturingmethod of the TFT substrate of the TFT liquid crystal display deviceaccording to one embodiment of the present invention up to thecompletion of the second photolithography step.

[0074]FIG. 7 is a cross-sectional view for explaining the manufacturingmethod of the TFT substrate of the TFT liquid crystal display deviceaccording to one embodiment of the present invention up to thecompletion of the third photolithography step.

[0075]FIG. 8 is a cross-sectional view for explaining the manufacturingmethod of the TFT substrate of the TFT liquid crystal display deviceaccording to one embodiment of the present invention up to thecompletion of the fourth photolithography step.

[0076]FIG. 9 is a cross-sectional view for explaining the manufacturingmethod of the TFT substrate of the TFT liquid crystal display deviceaccording to one embodiment of the present invention up to thecompletion of the fifth photolithography step.

[0077]FIG. 10 is an overall plan view of a LCD cell.

[0078]FIG. 11 is an overall plan view showing a state in which a PCBboard and a TAB are connected to the LCD cell.

[0079]FIG. 12 is a cross-sectional view of the TAB of the LCD cell and aneighborhood of a drain-side pull-out terminal portion.

[0080]FIG. 13 is a plan view expressing a schematic equivalent circuitof the TFT liquid crystal display device according to one embodiment ofthe present invention.

[0081]FIG. 14 is a timing chart expressing driving waveforms of thepixel of the TFT liquid crystal display device according to oneembodiment of the present invention.

[0082]FIG. 15 is an explanatory view showing one example of the moduleconstitution of the present invention.

[0083]FIG. 16 is a view for explaining the relationship between thepolarizer and the initial orientation direction according to oneembodiment of the present invention.

[0084]FIG. 17 is a plan view of a pixel of a TFT liquid crystal displaydevice according to another embodiment of the present invention.

[0085]FIG. 18 is a cross-sectional view of an essential part taken alonga line 18-18′ in FIG. 17.

[0086]FIG. 19 is a plan view of a pixel of a TFT liquid crystal displaydevice according to another embodiment of the present invention.

[0087]FIG. 20 is a cross-sectional view of an essential part taken alonga line 20-20′ in FIG. 19.

[0088]FIG. 21 is a plan view of a pixel of a TFT liquid crystal displaydevice according to another embodiment of the present invention.

[0089]FIG. 22 is a cross-sectional view of an essential part taken alonga line 22-22′ in FIG. 21.

[0090]FIG. 23 is a cross-sectional view of an essential part taken alonga line 23-23′ in FIG. 21.

[0091]FIG. 24 is a plan view of a pixel of a TFT liquid crystal displaydevice according to another embodiment of the present invention.

[0092]FIG. 25 is a cross-sectional view of an essential part taken alonga line 25-25′ in FIG. 24.

[0093]FIG. 26 is a plan view of a pixel of a TFT liquid crystal displaydevice according to another embodiment of the present invention.

[0094]FIG. 27 is a cross-sectional view of an essential part taken alonga line 27-27′ in FIG. 26.

[0095]FIG. 28 is a cross-sectional view of an essential part taken alonga line 28-28′ in FIG. 26.

[0096]FIG. 29 is a schematic view of a liquid crystal television set towhich the present invention is applied.

[0097]FIG. 30 is a schematic view of a liquid crystal monitor to whichthe present invention is applied.

[0098]FIG. 31 is a schematic view of an integral type personal computerto which the present invention is applied.

DETAILED DESCRIPTION

[0099] Typical structures which constitute features of the presentinvention are explained hereinafter in conjunction with followingembodiments.

[0100] (Embodiment 1)

[0101]FIG. 1 to FIG. 5 are a plan view and cross-sectional views of apixel according to a liquid crystal display device of one embodiment ofthe present invention. FIG. 2, FIG. 3 and FIG. 4 are cross-sectionalviews taken along cut lines indicated by chain lines as 2-2′, 3-3′ and4-4′ in FIG. 1 respectively. In these drawings, to facilitate theunderstanding of the cut portions, numerals are surrounded by circles soas to indicate the cut portions. The drawings show essential parts forexplanation purpose and orientation films are omitted from somedrawings. Further, the counter-substrate-side constitution is alsoomitted from some drawings. Hereinafter, these drawings are explained insequence.

[0102]FIG. 1 shows a schematic planar pattern of the pixel. One pixel isconfigured such that the pixel is surrounded by neighboring gate linesGL and neighboring drain lines DL. The gate line GL also functions as agate electrode for a TFT formed of a polysilicon PSI and supplies avoltage which turns ON the TFT. The drain line supplies current to thepolysilicon PSI. That is, a video voltage (drain voltage) which isapplied at the timing that the gate line GL supplies an ON voltage issupplied to the liquid crystal capacitance or the holding capacitance ofone pixel and, eventually, the potentials of a metal pixel electrode SPMand a transparent pixel electrode SPT which is connected to the metalpixel electrode SPM assume the video potential.

[0103] The flow of the electric current leads to the polysilicon PSIfrom the drain line DL through a first contact hole CNT1 and theelectric current which flows in the polysilicon PSI flows into the metalpixel electrode SPM through a second contact hole CNT2. Further, theelectric current reaches a transparent pixel electrode SPT on theinsulating film from the metal pixel electrode SPM through a thirdcontact hole CNT3.

[0104] In FIG. 1, the drain line DL increases a width thereof locally ata periphery of the contact hole CNT1 which connects the drain line DLand the polysilicon PSI. Due to such a constitution, it is possible torealize the reduction of the connection resistance of the contact holeCNT1 and the stable contact. It is needless to say that the drain lineDL can have the uniform width throughout the length provided that thenormal contact is ensured.

[0105] The common electrode potential of another electrode whichconstitutes the liquid crystal capacitance or the holding capacitancetogether with the pixel electrode is applied through a following path.The common potential is, first of all, applied to a lateral commonelectrode line CLMG which is arranged at the approximately centerbetween the neighboring gate lines GL and a vertical common electrodeline CLMD which is arranged at the approximately center between theneighboring drain lines DL. The electricity is supplied to these commonelectrode lines CLMG, CLMD from a power supply outside a screen.Further, the lateral common electrode line CLMG is made of the samematerial and is formed by the same steps as the gate lines GL. On theother hand, the lateral common electrode line CLMD is made of the samematerial and is formed by the same steps as the drain lines DL.

[0106] One of the features of this planar structure lies in a point thatthe lateral common electrode line CLMG and the vertical common electrodeline CLMD are connected to each other via a fourth contact hole CNT4.Accordingly, when viewed from the screen region of the liquid crystaldisplay device, there exists a state in which the common electrode lineshaving low resistance are connected in a mesh pattern so that wiringdelay can be made extremely small. These common electrode lines CLMG,CLMD which are made of metal play a role of mainly supplying thepotential to the holding capacitance which is defined in an area regionwhere the metal pixel electrode SPM and the lateral common electrodeline CLMG are overlapped to each other in plane. The insulating filmwhich forms the holding capacitance is an interlayer insulating filmwhich insulates and separates the gate line GL and the drain line DL. Inthis manner, by forming the vertical common electrode line CLMD on thesame layer as the drain line DL, by forming the lateral common electrodeline CLMG on the same layer as the gate line GL, and by connecting bothcommon electrode lines CLMD, CLMG at each pixel, the parasiticcapacitance formed between the gate line GL, the drain line DL and thecommon electrode lines CLMD, CLMG can be reduced and hence, the supplyof common electrode potential can be made stable including anadvantageous effect brought about by the supply of electricity in amatrix array whereby the display which largely reduces the luminanceirregularities and the smear can be realized. Further, with respect tothe arrangement of the common electrode lines CLMD, CLMG, since thevertical common electrode line CLMD is arranged in the directionparallel to the drain line DL on the same layer and the lateral commonelectrode line CLMG is arranged in the direction parallel to the gateline GL on the same layer, the probability of occurrence ofshort-circuiting between the electrodes on the same layer can be reducedwhereby the yield factor can be enhanced. Further, video signalssupplied by the drain line include the influence of the gate lines GLdue to the capacitive coupling since the drain line DL is arranged in astate that the drain line traverses a large number of gate lines GL. Inthis embodiment, however, by forming the vertical common electrode lineCLMD on the same layer as the drain line DL, the common potentialsupplied from the vertical direction receives the influence from thegate line GL similar to that of the video signals. As a result, thevoltage written in the holding capacitance portion gives rise to adifferential voltage between voltages and hence, it is possible toobtain an advantageous effect that the differential voltage works in thedirection to cancel the influence of the gate lines GL. Accordingly, thereduction of the display irregularities and the reduction of the smearcan be achieved. Further, as can be understood clearly from FIG. 3, acontact hole CNT4 which connects the lateral common electrode line CLMGand the vertical common electrode line CLMD has an upper portion thereofprotected by a protective insulating film PAS and hence, the reliabilityof the connection portion can be enhanced. Further, the leveling isperformed using an organic protective film FPAS and hence, the influenceto the rubbing can be obviated. Further, by forming the lateral commonelectrode line CLMG using the gate line layer and by forming thevertical common electrode line CLMD using the drain line layer, it ispossible to form the contact hole CNT4 between them using an inorganicinsulating film. Accordingly, the size of the contact hole CNT4 can bereduced thus realizing the further enhancement of the numericalaperture.

[0107] On the other hand, each pixel region is provided with, besidesthe common electrode lines CLMG, CLMD which are made of metalelectrically connected in a mesh pattern in the above-mentioned manner,the transparent common electrodes CLT which are arranged over the gatelines GL and the drain lines DL above the pixel region by way of aninsulating film having the low dielectric constant such that thetransparent common electrodes CLT shield these lines GL, DL. Between theneighboring pixels, the transparent common electrodes CLT are formed ina mesh pattern. The transparent common electrodes CLT are bifurcatedinto the inside of the pixel and play a role of common electrodes whichdrive the liquid crystal together with the pixel electrode SPT. Thetransparent common electrodes CLT are not connected to the lateralcommon electrode line CLMG and the vertical common electrode line CLMDwhich are made of metal in the inside of the pixel but are connected tothem in the peripheral region of the screen. Further, while the lateraltransparent common electrode line CLMG and the vertical transparentcommon electrode line CLMD constitute lines which mainly charge theholding capacitance, the transparent common electrodes CLT play a roleof charging the liquid crystal capacitance. In the IPS liquid crystaldisplay device, the liquid crystal capacitance assumes a value which isdefined between the transparent common electrodes CLT and thetransparent pixel electrode SPT shown in FIG. 1, for example and hence,the value becomes not more than one half compared to the liquid crystalcapacitance of the TN type liquid crystal display device which forms theliquid crystal capacitance between electrodes formed over the majorregions of surfaces of substrates which face each other. As a result,even when the specification of the wiring resistance of the transparentcommon electrodes CLT exhibits a relatively high value, it is possibleto charge the liquid crystal capacitance. Accordingly, varioustransparent conductors, that is, ITO (Indium-Tin-Oxide), IZO(Indium-Zinc-Oxide), ITZO (Indium-Tin-Zinc-Oxide), SnO₂, In₂O₃ and thelike can be used. Further, it is possible to obtain the high imagequality by suppressing the luminance irregularities and the smear.

[0108] The potential of the above-mentioned common electrode and commonelectrode lines is set to the approximately intermediate potential ofthe pixel potential which is alternated every frame (explained in detaillater in conjunction with FIG. 14). In the liquid crystal display deviceusing the TFTs, it is preferable to set the intermediate potential bytaking the fluctuation generated by a jump voltage into consideration.The liquid crystal capacitance and the holding capacitance are formed bythe pixel electrode potential and the common electrode potential and, atthe same time, the electric field is generated by the potentialdifference between potentials in the inside of the liquid crystal layer,and images are displayed by the video voltages supplied from the drainline DL and the common voltage. Main transmitting portions areconstituted of four opening portions formed along a line 2-2′ in FIG. 1.

[0109] Hereinafter, the constitutions of respective parts are explainedin detail in conjunction with the cross-sectional views. FIG. 2 is across-sectional view taken along a line 2-2′ in FIG. 1 and shows aportion which traverses one pixel region between the neighboring drainlines DL. A background insulating film ULS which is constituted of aSi₃N₄ film having a film thickness of 50 nm and a SiO₂ film having afilm thickness of 120 nm is formed over an alkalifree TFT glasssubstrate GLS1 having a strain point of approximately 670 degreecentigrade. The background insulating film ULS has a role of preventingthe diffusion of impurities such as Na or the like from the TFT glasssubstrate GLS1. A gate insulating film GI which is formed of SiO₂ isformed over the background insulating film ULS.

[0110] An interlayer insulating film ILI made of SiO₂ is formed suchthat the film ILI covers all of the above-mentioned parts or members.The drain line DL formed of a three-layered metal film such as Ti/Al/Tiis formed over the interlayer insulating film ILI. The metal pixelelectrode SPM which is formed of the same material and by the same stepsas the above-mentioned drain lines DL constitutes an electrode whichsupplies the pixel potential via the second contact hole CNT2 of the TFTin FIG. 1. Further, on the same layer, the vertical common electrodeline CLMD which is formed of the same material and by the same steps asthe drain lines DL is formed in parallel with the drain lines DL andplays a role to supply the common potential to the holding capacitance.

[0111] Onto the drain line DL, a protective insulating film PAS made ofSi₃N₄ having a film thickness of 200 nm and an organic protective filmFPAS containing acrylic resin as a main component and having a filmthickness of 2 μm are applied. Over the organic protective film FPAS,first of all, the transparent common electrode line CLT made of indiumtin oxide (ITO) and having a width wider than that of the drain line DLis formed. The transparent pixel electrode SPT made of ITO which isformed by the same step and of the same material is also formed over theorganic insulating film FPAS.

[0112] In the above description, the materials for forming respectivelines are not particularly limited.

[0113] The main transmitting regions are four regions consisting of (1)a region formed between the transparent common electrode line CLT overthe drain line DL and the transparent pixel electrode SPT, (2) a regionformed between the above-mentioned transparent pixel electrode SPT andthe transparent common electrode line CLT extending upwardly anddownwardly from the gate line GL in a plan view shown in FIG. 1 suchthat the transparent common electrode line CLT covers the verticalcommon electrode line CLMD, (3) a region formed between theabove-mentioned transparent common electrode line CLT and thetransparent pixel electrode SPT, and (4) a region arranged between thetransparent pixel electrode SPT and the transparent common electrodeline CLT arranged over the drain line DL. The above-mentionedtransparent pixel electrode SPT and the transparent common electrodeline CLT constitute electrodes which drive the liquid crystal.

[0114] On the other hand, a substrate which faces the TFT glasssubstrate GLS1 in an opposed manner and seals liquid crystal LC togetherwith the TFT glass substrate GLS1 is a color filter (CF) substrate GLS2.Color filters (FIL) which are constituted of organic film materialdispersing pigments for performing color display at a liquid crystalside thereof are formed over the CF glass substrate GLS2. These colorfilters FIL express the transmitting lights of blue (B), red (R), green(G) corresponding to colors allocated to respective pixels. For example,the color filter which expresses the transmitting light of red (R) isindicated by FIL (R). On inner sides of these color filters FIL, anovercoat film OC made of organic material is formed. Although theovercoat film OC may be eliminated, the provision of the overcoat filmOC is desirable to enhance the flatness. Orientation films OLI areprinted on respective surfaces of the CF glass substrate GLS2 and theTFT glass substrate GLS1 which are brought into contact with the liquidcrystal LC and a given rubbing is applied to these orientation films OLIso as to control the initial orientation direction of the liquid crystalLC. Further, to respective outer surfaces of the CF glass substrate CLS2and the TFT glass substrate GLS1, polarizers POL are respectivelylaminated. These polarizers POL are formed in a so-called crossed Nicolsstate in which polarization axes cross each other between the glasssubstrates.

[0115] The relationship of angle between the rubbing direction and thepolarizer is shown in FIG. 16. One polarization axis PD2 is arranged inthe same direction as the gate line GL and the other polarization axisPD1 is arranged in the direction perpendicular to the gate line GL.Further, the rubbing directions RD of both upper and lower substratesGLS1, GLS2 are arranged in the direction perpendicular to the gate lineGL. Due to such a relationship, an arrangement of normally black mode isobtained. Further, a multi-domain is designed by adopting a bent-shapepixel pattern shown in FIG. 1, it is needless to say that anon-multi-domain is also included in the scope of the present invention.It is necessary to arrange the polarizers in a crossed Nicols state alsoin such a case.

[0116] In the cross section of the CF substrate GLS2, a so-called blackmatrix BM is not formed. The joining of colors of the color filters FILis performed over the transparent common electrode line CLT which isarranged to cover the drain lines DL.

[0117] One of the features of the cross-sectional structure of thisembodiment lies in that with the provision of the transparent pixelelectrode SPT and the transparent common electrode CPT over the organicinsulating film FPAS, one pixel has at least four divided openings (maintransmitting regions) with respect to the liquid crystal LC.

[0118] Another feature of the cross-sectional structure of thisembodiment lies in that, over the organic protective film FPAS, to applythe liquid crystal display voltage, the metal pixel electrode SPM, thevertical common electrode line CLMD and the drain line DL are arrangedbelow the transparent pixel electrode SPT and the transparent commonelectrode CLT which are arranged in a spaced-apart manner and have givenwidths respectively while sandwiching a laminated insulating film formedof the organic insulating film FAPS and the protective film PAStherebetween. The respective widths of the transparent electrodes SPT,CLT are set as follows.

[0119] The width of the transparent common electrode line CLT whichcovers the drain line DL is required to be at least two times largerthan the width of the drain line DL. This is because that in the IPSliquid crystal display device, basically, when an electric field otherthan the electric field generated by the common electrode potential andthe pixel potential is applied to the liquid crystal, the smear and thedomain occur and hence, a shielding thereof is necessary. On the otherhand, the widths of the transparent electrodes SPT, CLT over the metalpixel electrode SPM and the vertical common electrode line CLMD are notlimited to the widths of the metal pixel electrode SPM and the verticalcommon electrode line CLMD since these electrodes SPT, CLT assume thesame potential as the potential of the metal pixel electrode SPM and thevertical common electrode line CLMD arranged below the transparentelectrodes SPT, CLT. However, in the IPS liquid crystal display devicewhich adopts the positive-type liquid crystal material, the light doesnot pass over the transparent electrodes. This is because that thelateral electric field is not applied over the electrodes having thelarge width and hence, the liquid crystal molecules are not rotated. Afringe lateral electric field is applied to a region extending towardthe inside of the width from end portions of the transparent electrodesby 1.5 μm and hence, the light passes over this region. Taking theabove-mentioned points into consideration, the widths of the metal pixelelectrode SPM and the vertical common electrode line CLMD are basicallyset to values equal to or narrower than the widths of the transparentpixel electrode SPT and the transparent common electrode line CLTarranged over the metal pixel electrode SPM and the vertical commonelectrode line CLMD. Further, the wiring material of the vertical commonelectrode line CLMD is equal to the wiring material of the drain line DLand is basically a Ti/Al/Ti line which exhibits the low resistance. Thevertical common electrode line CLMD has a feature that even when thewidth thereof is set to a minimum value which is decided by a processrule, the wiring delay can be made small and hence, there is nopossibility that the numerical aperture is reduced. Particularly, inthis embodiment, the constitution that the vertical common electrodeline CLMD is arranged below the transparent electrode line CLT which isindispensable in the driving of the liquid crystal thus preventing anyfurther reduction of the numerical aperture also constitutes the featureof this embodiment.

[0120]FIG. 3 is a cross-sectional view taken along a line 3-3′ shown inFIG. 1. This cross-sectional view shows a cross section of the drainline DL—the first contact hole CNT1—the polysilicon layer PSI of theTFT—the second contact hole CNT2—the metal pixel electrode SPM which isarranged over the lateral common electrode line CLMG by way of theinterlayer insulating film ILI such that the metal pixel electrode SPMgets over the lateral common electrode line CLMG—the third contact holeCNT3—the fourth contact hole CNT 4 which connects the lateral commonelectrode line CLMG and the vertical common electrode line CLMD in theplan view shown in FIG. 1. The left side of the cross-sectional view inFIG. 3 shows the cross section of the TFT. The TFT constitutes aso-called MOS TFT having a gate insulating film GI in which the drainline DL and the metal pixel electrode SPM are respectively used asso-called drain electrode and source electrode, and the gate line GL isused as a gate electrode. The p-Si layer is formed over the backgroundinsulating film ULS. The drain line DL and the metal pixel electrode SPMare connected to a highly concentrated n-type layer PSI(n⁺) which isdoped with phosphorus of low-temperature polysilicon PSI as impuritiesthrough the first contact hole CNT1 and the second contact hole CNT2formed in the gate insulating film GI and the interlayer insulating filmILI. The highly concentrated n-type layer PSI(n⁺) is highly conductiveand functions as a wiring portion in a pseudo manner. On the other hand,the low-temperature polysilicon PSI below the gate line GL isconstituted of a p-type layer PSI(p) doped with boron as impurities andfunctions as a so-called semiconductor layer. The p-type layer PSI(p)performs a switching operation in which the p-type layer PSI(p) becomesconductive with the gate line GL at an ON potential and becomesnon-conductive at an OFF potential. When an ON voltage is applied to thegate line GL, below the gate insulating film GI which is arranged belowthe gate line GL, a potential formed at an interface of the p-type layerPSI(p) doped with boron as impurities with the gate insulating film GIis inverted so as to form a channel layer and the layer is convertedinto the n-type so that an ON current flows into the TFT and eventuallyan electric current flows into the metal pixel electrode SPM whereby theliquid crystal capacitance and the holding capacitance are charged. Theholding capacitance Cstg is formed in such a manner that, the lateralcommon electrode line CLMG is used as one electrode, an interlayerinsulating film ILI is used as the insulating film and the metal pixelelectrode SPM is used as the other electrode. The holding capacitanceCstg is set to hold the potential during the image display period(holding period) which is determined by the liquid crystal capacitancewith respect to a leak current which is increased by a pair of electronsand positive holes generated by irradiation of light by the backlightfor display from the TFT glass substrate GLS1 side to the polysiliconPSI of the TFT in FIG. 3. If this value can be set large, it is possibleto hold the uniformity over the display screen in an extremely favorablestate.

[0121]FIG. 4 is a cross-sectional view taken along a line 4-4′ inFIG. 1. This cross-sectional view mainly shows the cross-sectionalstructure ranging from the gate line GL, the low-temperature polysiliconPSI of the TFT and the transparent common electrode line CLT whichcovers these components to the transmitting region by way of the organicprotective film.

[0122] The cross-sectional structure shown in FIG. 4 comprises the gateline GL arranged at the left side and the transmitting region arrangedat the right side. The gate line GL and the low-temperature polysiliconPSI are covered with the transparent common electrode CLT formed overthe protective film PAS and the organic protective film FPAS. Thisprovision is adopted to prevent the occurrence of a phenomenon that withrespect to the potential of the gate line GL, the line of electric forceof the gate line GL is leaked to the transmitting region sandwiched bythe transparent common electrode CLT and the transparent pixel electrodeSPT thus inducing an erroneous display operation.

[0123] The feature of this structure lies in that the transparent commonelectrode line CLT which is arranged to cover the above-mentioned gateline GL and low-temperature polysilicon layer PSI exhibits anadvantageous effect such as an extremely high quality black matrix BMalthough the transparent common electrode line CLT is formed of atransparent electrode. As shown in FIG. 2, an electric field E whichdrives the liquid crystal is a lateral electric field between thetransparent common electrode line CLT and the transparent pixelelectrode SPT. In the IPS type liquid crystal display device, the liquidcrystal molecules LC are rotated by this lateral electric field thuschanging the transmissivity with respect to the orthogonal polarizerPOL. In the state that there is no electric field or the lateralelectric field is small, the polarizer is arranged in a crossed Nicolsstate and hence, the black display is exhibited. When the electric fieldis applied, the transmission of the elliptically polarized light isgenerated and light is transmitted in response to the electric field.Accordingly, in the region where there is no electric field or theelectric field is small, even when the transparent common electrode CLTis formed of a transparent electrode made of ITO, the backlight lightemitted from the TFT glass substrate GLS1 side is not transmitted and itis possible to obtain the favorable black state even when observed fromthe CF substrate GLS2 which is an observer side. On the other hand, inthe state that the voltage is applied, the lateral electric fieldcomponents in the fringe state is generated in the region starting fromthe end portion of the transparent electrode to the inside of theelectrode by approximately 1.5 μm (an example of the region when thetransparent common electrode line CLT is arranged over the gate line GLbeing indicated by WT in FIG. 4) and the lateral electric fieldcomponents contribute to the transmission of the light.

[0124] Accordingly, with respect to the image formed of the backlightlight from the TFT glass substrate GLS1 side, in the planar structureshown in FIG. 1, the transparent common electrode CLT having the widththereof set to a value which is sufficiently large to cover at least theTFT including the low-temperature polysilicon PSI and the gate line GL,when viewed by human naked eyes, makes a profile of each pixel clear andperforms a function similar to the BM to sharpen the image. In FIG. 4,in a WN region over the transparent common electrode CLT, that is, in aregion within 1.5 μm from an end portion of the transparent electrodewhich constitutes a transparent electrode single body, there existsubstantially no lateral electric field components and hence, thepolarized state of light receives no influence during the transmissionof light through the liquid crystal layer whereby the light is shieldedby the polarizer POL formed on the CF substrate GLS2. For example,although the low-temperature polysilicon is originally considered toappear in a state that the low-temperature polysilicon PSI is colored inred, the low-temperature polysilicon appears as the black matrix BM in acompletely black display state. In a region WR over the gate line GL,the light is completely shielded by the metal and hence, the region WRassumes the black state irrespective of the state of the electric field.

[0125] As shown in the cross-sectional view of FIG. 4, in the structureaccording to this embodiment, a conventional black matrix BM is notformed on the CF substrate GLS2. Accordingly, in the IPS liquid crystaldisplay device which adopts the structure of this embodiment, a step forforming the black matrix BM layer becomes unnecessary so that themanufacturing cost can be reduced. With respect to an external light,the above-mentioned transparent common electrode CLT plays a role of theblack matrix BM which exhibits the extremely favorable small reflection.This is an advantageous effect obtained by using the transparentelectrode as the light shielding layer. Further, since the lightshielding layer is mounted on the substrate which faces theobservation-side substrate in an opposed manner, the reflection isfurther reduced. In the region WN of the transparent common electrodeCLT, although the external light is absorbed by the transparent commonelectrode CLT per se, the protective film PAS, the organic protectivefilm FPAS and the like, since there is no metal layer which exhibits thehigh reflectivity, the reflection to the observer side is small. On theother hand, the material of the gate line GL is MoW and hence, thereexists a slight reflection compared to Al, for example. However, thelight passes the protective film PAS and the like formed above the gateline GL twice and receives the effect of the polarizer POL in thecrossed Nicols state and hence, the reflection can be suppressed to asmall value. In this manner, when the transparent common electrode CLTis used as the black matrix BM, it is possible to form the black matrixBM having an extremely small reflection. Further, since it isunnecessary to form the black matrix BM on the CF substrate GLS2, thetolerance of alignment of the upper and lower substrates is increasedthus realizing the enhancement of the productivity. Further, thedesigning which takes the misalignment into account is no longernecessary and hence, it is possible to use a region which has beenconventionally subjected to light shielding extra by the black matrix BMby estimating the tolerance of alignment based on the region whichrequires light shielding by the black matrix BM whereby the numericalaperture is enhanced. Further, the light shielding region at the endportion of the transparent electrode CLT can make the whole region ofthe electrode fall in a black display state when the black display isperformed, while the light shielding region ranging 1.5 μm from the endof the electrode becomes the transmitting region when the white displayis performed. Accordingly, between the black display state in which itis necessary to display image sharply and the white display state inwhich the bright display is necessary, the light shielding region iskinetically and automatically changed. That is, the light shieldinglayer made of the transparent electrode functions as a really idealblack matrix BM such that the light shielding region is broadened in theblack display and is narrowed in the white display. Accordingly, theenhancement of the clearness of images, the enhancement of contrast andthe enhancement of luminance which are considered to conflict each othercan be realized at the same time.

[0126] Subsequently, the manufacturing steps of the NMOS type TFT shownin FIG. 3 is explained in conjunction with FIG. 5 to FIG. 9 and FIG. 3.

[0127] After cleaning the alkalifree TFT glass substrate GLS1 having athickness of 0.7 mm, a size of 730 mm×920 mm and having a strain pointof approximately 670 degree centigrade, the background insulating filmULS is formed by laminating a Si₃N₄ film and a SiO₂ film over thealkalifree TFT glass substrate GLS1, wherein the Si₃N₄ film having afilm thickness of 50 nm is formed by a plasma CVD method using a mixedgas of SiH₄, NH₃ and N₂ and, thereafter, the SiO₂ film having a filmthickness of 120 nm is formed by a plasma CVD method using a mixed gasof tetraethoxysilane and O₂. The background insulating film ULS isprovided for preventing the diffusion of Na from the TFT glass substrateGLS1 to the polycrystalline silicon film. The formation temperature ofboth of the Si₃N₄ and SiO₂ films is 400 degree centigrade. Here,although the polycrystalline silicon is representatively used as thesemiconductor layer, the semiconductor layer may be formed ofmacro-crystalline silicon, continuous grain boundary silicon oramorphous silicon.

[0128] Subsequently, an approximately intrinsic hydrated amorphoussilicon film having a film thickness of 50 nm is formed by a plasma CVDmethod using a mixed gas of SiH₄ and Ar. The film forming temperature is400 degree centigrade and the hydrogen quantity immediately after filmforming is approximately 5 at %. Subsequently, the substrate is annealedfor approximately 30 minutes at a temperature of 450 degree centigradeso as to dissipate hydrogen in the hydrated amorphous silicon film. Thehydrogen quantity after annealing is approximately 1 at %.

[0129] Subsequently, an excimer laser beam LASER having a wave length of308 nm is irradiated to the amorphous silicon film at a fluence of 400mJ/cm² so as to melt and recrystallize the amorphous silicon film thusobtaining the approximately intrinsic polycrystalline silicon film.Here, the laser beam has a thin elongated line shape of a width of 0.3mm and a length of 200 mm. The laser beam is irradiated to the substrateby moving the substrate at a pitch of 10 μm in the directionsubstantially perpendicular to the longitudinal direction of the beam.The irradiation is performed in the nitrogen atmosphere.

[0130] A given resist pattern is formed over the polysilicon film PSI bya usual photolithography method and the polysilicon film PSI is formedinto a given shape by a reactive ion etching method using a mixed gas ofCF₄ and O₂ (FIG. 5).

[0131] Subsequently, a SiO₂ film having a film thickness of 100 nm isformed by a plasma CVD method using a mixed gas of tetraethoxysilane andoxygen thus obtaining the gate insulating film GI. Here, the mixingratio of tetraethoxysilane and O₂ is set to 1:50 and the film formingtemperature is set to 400 degree centigrade. Subsequently, B ions areimplanted at an acceleration voltage of 33 Kev and a dosed quantity of1E12 (cm⁻²) by an ion implantation method so as to form the polysiliconfilm PSI(p) in the channel region of the n-type TFT.

[0132] Then, a metal line, that is, a Mo film or a MoW film, forexample, having a film thickness of 200 nm is formed by a sputteringmethod and, thereafter, a given resist pattern is formed over the Mofilm by a usual photolithography method. Thereafter, the Mo film isformed into a given shape by a wet etching method using a mixed acidthus obtaining the scanning line GL and the second lateral commonelectrode line CLMG.

[0133] While leaving the resist pattern used for etching as it is, Pions are implanted at an acceleration voltage of 60 Kev and a dosedquantity of 1E15 (cm⁻²) by an ion implantation method so as to form thesource and drain regions PSI(n⁺) of the n-type TFT (FIG. 6). Althoughthe n-type TFT in which the source and drains are respectively formed ofthe (n+)-type low-temperature polysilicon film PSI(n+) and thepolysilicon film PSI(p) of p-type channel region is formed in accordancewith the above-mentioned steps, it is possible to reduce a leakingcurrent of the TFT by forming an n-type LDD region whose P ionconcentration is smaller than that of the (n+)-type region between thep-type region and the (n+)-type region (not shown in the drawing). Thatis, after removing the resist pattern used for etching, P ions areimplanted again at an acceleration voltage of 65 Kev and a dosedquantity of 2E13 (cm⁻²) by an ion implantation method so as to form theLDD region of the n-type TFT. The length of the LDD region is determinedbased on a side etching quantity at the time of performing the wetetching of Mo. In this embodiment, the length of the LDD region isapproximately 0.8 μm. The length can be controlled by changing theover-etching time of Mo.

[0134] Subsequently, the implanted impurities are activated by a rapidthermal annealing (RAT) method which irradiates light of an excimer lampor a metal halide lamp to the substrate. By performing annealing usinglight which contains a large quantity of ultraviolet rays irradiatedfrom the excimer lamp or the metal halide lamp or the like, it ispossible to selectively heat only the polysilicon layer PSI so that anydamage which may be caused by heating the glass substrate can beobviated. The activation of the impurities may be performed by the heattreatment at a temperature of approximately 450 degree centigradeprovided that shrinkage, bending deformation or the like of substrate issmall so that they do not cause any problem (FIG. 6).

[0135] Subsequently, a SiO₂ film having a film thickness of 500 nm isformed by a plasma CVD method using a mixed gas of tetraethoxysilane andoxygen thus obtaining an interlayer insulating film ILI. Here, a mixingratio of tetraethoxysilane and oxygen is 1:5 and the film formingtemperature is 350 degree centigrade.

[0136] Then, after forming a given resist pattern, by a wet etchingmethod using a mixed acid, the first contact hole CNT1, the secondcontact hole CNT2 and the fourth contact hole CNT4 shown in a plan viewof FIG. 1 are formed in the above-mentioned interlayer insulating film(FIG. 7).

[0137] Subsequently, by a sputtering method, a Ti film having a filmthickness of 50 nm, an Al—Si alloy film having a film thickness of 500nm and a Ti film having a film thickness of 50 nm are sequentiallyformed by lamination. Then, a given resist pattern is formed.Thereafter, by a reactive ion etching method using a mixed gas of BCl₃and Cl₂, a collective etching is performed thus obtaining the drain lineDL, the metal pixel electrode SPM and the vertical common electrode lineCLMD (FIG. 8).

[0138] The protective film PAS which is a Si₃N₄ film having a filmthickness of 300 nm is formed by a plasma CVD method using a mixed gasof SiH₄, NH₃ and N₂. Further, an acrylic photosensitive resin filmhaving a film thickness of approximately 3.5 μm is applied by a spincoating method and exposure and development are performed using a givenmask thus forming through holes in the acrylic resin. Then, the acrylicresin is baked for 20 minutes at a temperature of 230 degree centigradethus obtaining the leveled organic protective film FPAS having a filmthickness of 2.0 μm. Subsequently, using the through hole pattern formedin the organic protective film FPAS as a mask, the Si₃N₄ film arrangedbelow the organic protective film FPAS is processed by a reactive ionetching method using CF₄ thus forming the third contact hole CNT3 in theSi₃N₄ film (FIG. 9).

[0139] By processing the insulating film which constitutes the layerbelow the organic protective film FPAS using the organic protective filmFPAS as a mask, films in two layers can be patterned in onephotolithography step so that the entire steps can be simplified.

[0140] Finally, the transparent conductive film such as an ITO filmhaving a film thickness of 70 nm is formed by a sputtering method. Then,by a wet etching using a mixed acid, the transparent conductive film isprocessed in a given shape thus forming the transparent common electrodeline CLT and the transparent pixel electrode SPT whereby the activematrix substrate is completed (FIG. 3). As described above, thepolycrystalline silicon TFT is formed by performing the photolithographysteps 6 times or more.

[0141] Subsequently, the planar structure of the overall appearance ofthe liquid crystal panel is explained. FIG. 10 is a plan view of anessential part around a matrix (AR) of a display panel including upperand lower glass substrates GLS1, GLS2. In manufacturing the panel, whenthe panel is of a small size, for enhancing the throughput, a pluralityof devices are simultaneously processed on a sheet of glass substrateand, thereafter, the glass substrate is divided. On the other hand, whenthe panel is of a large size, for enabling the common use of amanufacturing installation, a glass substrate which is standardized forany types of panels is processed and is reduced into a size whichmatches each type of panel and the glass substrate is cut after makingthe glass substrate pass through a series of steps.

[0142]FIG. 10 shows the latter case and shows a state in which the upperand lower substrates GLS1, GLS2 are already cut. In both cases, in acompleted state, the size of the upper substrate GLS2 is made smallertoward the inside than the lower side substrate GLS1 such that a portion(upper side in the drawing) where groups of external connectionterminals Tg, Td are present is exposed. With respect to the groups ofterminals Tg, Td, the group of terminals Tg are the connection terminalsfor power supply and timing data which are supplied to a scanningcircuit GSCL of the low-temperature polysilicon TFT which are arrangedat left and right sides of the display region AR on the TFT glasssubstrate GLS1. The group of terminals Td are connection terminals forsupplying video data or power source data to a video signal circuit DDCof the low-temperature polysilicon TFT formed on the TFT glass substrateGLS1 and over an upper portion of the display region AR. These groups ofterminals are named by arranging a plurality of lead line portions pertape carrier package TCP (FIG. 11) on which an integrated circuit chipsCHI are mounted. The lead lines extending from matrix portions ofrespective groups to external connection terminal portions through thevideo signal circuit DDC are inclined as these lead lines approach bothends. Such an arrangement is provided for matching the arrangement pitchof the package TCP and the connection terminal pitch at respectivepackages TCP with the arrangement pitch of the video signal terminals Tdof the display panel.

[0143] A seal pattern SL for sealing the liquid crystal LC is formedbetween the transparent glass substrates GLS1, GLS2 along peripheries ofthese substrates GLS1, GLS2 except for a liquid crystal filling portINJ. The sealing material is, for example, made of epoxy resin.

[0144] The orientation films ORI whose cross-sectional structure isshown in FIG. 2 are formed in the inside of the seal pattern SL. Theliquid crystal LC is sealed in a region defined by the lower orientationfilm ORI and the upper orientation film ORI which set the direction ofliquid crystal molecules and the seal pattern SL.

[0145] The liquid crystal display device is assembled such that varioustypes of layers are laminated at the lower transparent TFT glasssubstrate GLSI side and the upper transparent CF glass substrate GLS2side separately, the seal pattern SL is formed at the substrate GLS2side, the lower transparent glass substrate SUB1 and the uppertransparent glass substrate GLS2 are superposed each other, the liquidcrystal LC is filled through the liquid crystal filling port INJ formedin the sealing material SL, the liquid crystal filling port INJ isplugged by epoxy resin or the like, and the upper and lower substratesGLS1, GLS2 are cut.

[0146]FIG. 11 is a plan view showing a state in which the tape carrierpackages TCP which mount the video signal driving ICs on the displaypanel shown in FIG. 10 and the signal circuit DDC which is formed overthe TFT substrate GLS1 using the low-temperature polysilicon TFT areconnected to each other and a state in which the scanning circuit GSCLwhich is formed over the TFT substrate GLS1 using the low-temperaturepolysilicon TFT and the outside are connected to each other.

[0147] TCP indicates the tape carrier package on which driving IC chipsare mounted by a tape automated bonding method (TAB) and PCB1 indicatesa driving circuit board on which the above-mentioned TCP, a TCONconstituting a control IC, a power supply amplifier, resisters,capacitors and the like are mounted. CJ indicates a connector connectionportion for introducing signals and power supply from a personalcomputer or the like.

[0148]FIG. 12 is a cross-sectional view of an essential part showing astate in which the tape carrier package TCP is connected to the signalcircuit terminal Td of the liquid crystal display panel. The tapecarrier package TCP is connected to the liquid crystal display panelthrough an anisotropic conductive film ACF. The tape carrier package TCPhas an output terminal thereof electrically connected to the connectionterminal Td at the panel side. The tape carrier package TCP is formed soas to cover an opening portion formed in the protective film PAS and theorganic protective film FPAS of the TFT and is connected to thetransparent electrode ITO which is formed in the same manner as thetransparent common electrode line CLT. The gap defined between the upperand lower glass substrates GLS1, GLS2 outside the seal pattern SL isprotected by epoxy resin EPX or the like after cleaning. Silicone resinis further filled between the tape carrier package TCP and the upper CFsubstrate GLS2 so as to ensure the multiple protection (not shown in thedrawing). Further, the gap defined for filling the liquid crystal LCbetween the upper and lower glass substrates GLS2, GLS1 has a heightthereof determined by support columns SPC formed of an organic film orfibers.

[0149] A wiring chart between an equivalent circuit of a display matrixportion and a peripheral circuit around the equivalent circuit is shownin FIG. 13. In the drawing, DL indicates drain lines, wherein numeralsin the symbols DL1, DL2 and DL3 indicate the order of the arrangement ofthe drain lines (video signal lines) within the screen from the leftside of the screen. Suffixes R, G and B are respectively addedcorresponding to red, green and blue pixels. GL indicates gate lines,where in numerals in the symbols GL1, GL2 indicate the order of thearrangement of the gate lines within the screen from the upper side ofthe screen. Suffixes 1, 2 are added in accordance with the order ofscanning timing. CLX indicates lateral common electrode lines CLMG,wherein numerals in the symbols CLX1, CLX2 indicate the order ofarrangement of the lateral common electrode lines CLX within the screenfrom the upper side of the screen. On the other hand, CLY indicatesvertical common electrode lines CLMD and numerals in the symbols CLY1,CLY2 indicate the order of arrangement of the vertical common electrodelines CLY within the screen from the left side of the screen.

[0150] The gate lines GL (suffixes being omitted) are connected to thescanning circuit GSCL on the glass substrate and electricity and timingsignals are supplied to the scanning circuit from a power supply and atiming circuit SCC which are formed over a printed circuit board PCBarranged outside the glass substrate. In the above-mentionedconstitution, to the scanning circuit formed over the glass substratewhich is constituted of the low-temperature polysilicon TFT, electricityis supplied from both left and right sides with respect to one gate line(scanning line) to enhance the redundancy. However, electricity may besupplied to the scanning circuit from one side corresponding to the sizeof the screen or the like.

[0151] On the other hand, the supply of electricity is performed fromthe signal circuit DDC which is formed over the glass substrate andconstituted of the low-temperature polysilicon TFT. The signal circuitDDC has a function of distributing the video data from the circuitconstituted of the video signal circuit IC on the glass substrate inresponse to color data of R, G, B. Accordingly, the number of connectionterminals from the signal circuit on the glass substrate is one third ofthe number of the drain lines within the screen.

[0152] Further, in this embodiment, the common electrode lines areconstituted of the lateral transparent common electrode lines CLX(CLMG),the vertical common electrode lines CLY (CLMD) and the transparentcommon electrodes CLT. As shown in FIG. 1, the lateral common electrodelines CLX and the vertical common electrode lines CLY are connectedwithin the pixel and form the metal wiring in a matrix array. Thelateral common electrode lines CLX are pulled out to the left and rightsides of the screen and are collectively connected to a common electrodebus line CLB having low impedance and, thereafter, are connected to thepower supply and the timing circuit SCC. The vertical common electrodelines CLY are pulled out to the bottom side of the screen and arecollectively connected to a common electrode bus line CLB having lowimpedance and, thereafter, are connected to the power supply and thetiming circuit SCC in the same manner. As shown in FIG. 1, thetransparent electrode lines CLT are not connected with the lateralcommon electrode line CLX and the vertical common electrode line CLYwithin the screen. However, on the periphery of the screen, thetransparent electrode lines CLT are connected with the lateral commonelectrode line CLX in the left and right direction and are connectedwith the vertical common electrode line CLY on the bottom portion and,thereafter, are connected to the common electrode bus lines CLB and areconnected to the external power supply and the timing circuit SCC.Although not shown in FIG. 13, the common electrode lines are arrangedin a matrix array. The common electrode lines give the common potentialto the pixels in the screen.

[0153] The low-temperature polysilicon TFT within the screen is ann-type TFT. The display is performed by applying a gate voltage to thegate lines GL and by supplying a drain voltage (data) which is suppliedto the drain lines DL at the timing of supplying the gate voltage to thegate lines GL to the liquid crystal capacitance Clc between the drainline DL and the common electrode lines CLT. To enhance the ability tomaintain the potential of the liquid crystal capacitance Clc during thedisplay period, the holding capacitance Cstg is formed between thelateral common electrode line CLMG and the metal pixel electrode SPM asshown in FIG. 3. CC indicates an inspection circuit formed of alow-temperature polysilicon TFT which inspects the disconnection of thedrain lines DL. CPAD indicates an inspection terminal.

[0154]FIG. 14 shows driving waveforms of the liquid crystal displaydevice of the present invention. FIG. 14 shows an example when thecommon electrode voltage Vcom is a direct current voltage. The gatevoltage Vg sequentially scans every gate line. When a voltage obtainedby adding a threshold voltage of the low-temperature polysilicon TFT ofthe pixel is applied to the drain potential Vd, the pixel TFT assumes anON state and the gate voltage Vg is charged into the liquid crystalcapacitance Clc shown in FIG. 13. The above-mentioned common electrodevoltage Vcom, the gate voltage Vg, and the drain voltage Vd arerespectively applied to the lateral common electrode lines CLX, thevertical common electrode lines CLY shown in FIG. 13 and the transparentcommon electrode line CLT, the gate lines GL and the drain lines DLshown in FIG. 1. In this embodiment, the drain voltage Vd indicates avoltage which is used when a white display is performed at a liquidcrystal display in a normal black mode, for example, wherein the gateline is selected every one line and the polarity is inverted to the plusside or the minus side with respect to the common electrode voltage Vcomevery line. Although the pixel potential Vp is charged into the liquidcrystal capacitance Clc through the TFT, the pixel potential Vp isinverted with respect to the common electrode potential Vcom at odd oreven frames. With respect to the gate line GL of the TFT at a specificaddress, when the gate line GL is selected and the gate voltage Vgbecomes larger than the drain voltage Vd, the potential corresponding tothe images is charged into the liquid crystal capacitance Clc. However,as mentioned above, in the subsequent frame, the potential of liquidcrystal capacitance Clc must be held until the drain voltage Vd invertedwith respect to the common electrode potential Vcom is applied. Thisholding rate is lowered when an OFF (leak) current of the TFT isincreased. To prevent the lowering of the holding rate, it is necessaryto set the holding capacitance Cstg of the equivalent circuit shown inFIG. 13 to a large value. Assuming that the holding capacitance Cstg isset to a large value, when the parasitic capacitance of the commonelectrode lines is large, the wiring delay is increased and theluminance irregularities, the smear, the image retention or flickers aregenerated. Further, it is impossible to maintain the uniformity ofdisplay on the screen. However, as shown in the plan view of FIG. 1 andthe cross-sectional view of FIG. 3, in this embodiment, the lateralcommon electrode lines CLMG and the vertical common electrode lines CLMDwhich are made of metal material are connected in the screen in a matrixarray thus reducing the resistance. On the other hand, the transparentcommon electrodes CLT are connected between the pixels over the organicinsulating film-within the screen, while the transparent commonelectrodes CLT and the metal common electrode lines CLMG, CLMD are notdirectly connected to each other within the screen. However, thetransparent common electrodes CLT are served for merely charging theliquid crystal capacitance and hence, the material having a relativelyhigh resistance can be used as the material of the transparent commonelectrodes CLT as mentioned previously. Further, outside the screen, thetransparent common electrodes CLT are connected to the common electrodebus line CLB having low impedance shown in FIG. 13 so that theresistance is further reduced. Due to such advantageous effects,according to this embodiment, even when the holding capacitance Cstg isincreased, it is possible to enhance the uniformity of image quality ofthe screen.

[0155]FIG. 15 is an exploded perspective view showing respectiveconstitutional parts of a liquid crystal display module MDL. SHDindicates a frame-like shield case (metal frame) made of a metal plate,LCW indicates a display window of the shield case SHD, PNL indicates aliquid crystal display panel, SPB indicates a light diffusion plate, LCBindicates a light guide body, RM indicates a reflection plate, BLindicates a backlight fluorescent tube and LCA indicates a backlightcase. The module MDL is assembled by laminating respective members inaccordance with the vertical arrangement relationship shown in thedrawing.

[0156] The module MDL has the whole structure thereof fixed by pawls andhooks mounted on the shield case SHD. The backlight case LCA isconfigured such that a backlight fluorescent lamp BL, the lightdiffusion plate SPB, the light guide body LCB and the reflection plateRM can be accommodated therein. Light emitted from the backlightfluorescent tube BL which is arranged along a side surface of the lightguide body LCB is formed into a uniform backlight on a display screenthrough the light guide body LCB, the reflection plate RM and the lightdiffusion plate SPB and the backlight is irradiated to the liquidcrystal display panel PNL side. The backlight fluorescent tube BL isconnected to an inverter printed circuit board PCB2 which constitutes apower supply of the backlight fluorescent tube BL.

[0157] (Embodiment 2)

[0158]FIG. 17 is a plan view showing the pixel of the second embodimentof the present invention and FIG. 18 is a cross-sectional view takenalong a cut line indicated by chain lines as 18-18′ in FIG. 17. In thedrawing, to facilitate the understanding of the cut portions, numeralsare surrounded by circles so as to indicate the cut portion.

[0159]FIG. 17 shows an IPS mode pixel pattern which has 4 maintransmitting portions in the direction which traverses the drain linesDL in the same manner as the embodiment 1. Although the constitution ofthis embodiment is similar to the constitution of the embodiment 1, theimportant feature of this embodiment lies in that as the commonelectrode line which is made of metal, only the vertical commonelectrode lines CLMD are arranged. That is, the lateral common electrodelines CLDM which are arranged in the constitution shown in FIG. 1 areeliminated. That is, this embodiment adopts the new constitution forforming the holding capacitance. Further, due to such a constitution,the numerical aperture can be further enhanced compared to the numericalaperture of the constitution according to the embodiment 1.

[0160] The holding capacitance Cstg is formed in the following manner.First of all, the holding capacitance electrode STM which is formed bythe same step and formed of the same material as the gate line GL isprocessed in an island shape. The holding capacitance electrode STM isconnected to a vertical common electrode line CLMD via a fourth contacthole CNT4. On the other hand, a metal pixel electrode SPM which extendsfrom a second contact hole CNT of a TFT formed of low-temperaturepolysilicon PSI extends over the holding capacitance electrode STM. Theholding capacitance is formed of overlapped area portions of the metalpixel electrode SPM and the holding capacitance electrode STM whichoverlap each other by sandwiching an interlayer insulating film therebetween. The transparent pixel electrode SPT is connected to the metalpixel electrode SPM via a third contact hole CNT3 and hence, a pixelpotential is supplied to the liquid crystal. On the other hand, althougha transparent common electrode line CLT is not connected to the verticalcommon electrode line CLMD within the screen, the transparent commonelectrode lines CLT are connected to them outside the pixel region so asto supply the common potential to the liquid crystal.

[0161] Due to such a constitution, following two new advantageouseffects can be obtained. The first advantageous effect is that amongfour transmitting regions in a plan view of the pixel shown in FIG. 17,a new opening portion which is defined by the transparent electrode lineCLT which covers the drain line DL and the transparent pixel electrodeSPT at the inner side within the pixel is formed by eliminating thelateral common electrode line shown in FIG. 1 of the embodiment 1(region defined by lines LL, LR shown in FIG. 17). Due to such aconstitution, it is possible to provide the bright IPS type liquidcrystal display device. The second advantageous effect is that theparasitic capacitance of the drain line DL can be reduced by eliminatingthe lateral common electrode line CLMG which crosses the drain line DL.Accordingly, the number of division of a circuit incorporated in thedrain division circuit DDC shown in FIG. 13 can be increaed and hence,the number of components constituted of the TCPs shown in FIG. 11 can bereduced whereby the manufacturing cost can be reduced.

[0162]FIG. 18 is a cross-sectional view taken along a cut line 18-18′ inFIG. 17. The drain voltage which constitutes the video signal istransmitted to the low-temperature polysilicon PSI from the drain lineDL via the first contact hole CNT1. When the ON voltage is applied tothe gate line GL, the MOS type TFT is operated and the video voltage istransmitted to the metal pixel electrode SPM which is connected tolow-temperature polysilicon PSI via the second contact hole CNT2.Finally, the video voltage is transmitted to the transparent pixelelectrode SPT which is connected to the metal pixel electrode SPM viathe third contact hole CNT3 and forms the pixel potential whichconstitutes one of the liquid crystal capacitances. The common voltagewhich constitutes another potential for driving the liquid crystal isapplied to the transparent common electrode line CLT. A new openingportion indicated by LR in FIG. 17 constitutes a new transmitting regionwhich is formed by the lateral electric field applied to the transparentpixel electrode SPT and the transparent common electrode line CLT sothat it is possible to provide the bright liquid crystal display device.

[0163] Further, as can be understood from the drawing, the black matrixBM is not formed on the CF substrate GLS2 and the TFT formed of thelow-temperature polysilicon PSI and the gate line GL are covered withthe transparent common electrode line CLT which is arranged over theorganic protective film FPAS. Although the transparent common electrodeline CLT is a transparent electrode, the transparent common electrodeline CLT forms the region to which the lateral electric field is notapplied thus playing a role of the favorable black matrix BM.

[0164] Further, since the lateral common electrode line CLMG is selectedas the common electrode line to be eliminated in this embodiment, it ispossible to maintain the advantageous effect which is explained inconjunction with the embodiment 1, that is, the advantageous effect thatthe vertical common electrode line CLMD is formed on the same layer asthe drain line DL and traverses the gate lines GL and hence, the gatepotential with respect to the holding capacitance can be cancelled.

[0165] (Embodiment 3)

[0166]FIG. 19 is a plan view showing the pixel of the third embodimentof the present invention and FIG. 20 is a cross-sectional view takenalong a cut line indicated by chain lines as 20-20′ in FIG. 19. In thedrawing, to facilitate the understanding of the cut portions in thedrawing, numerals are surrounded by circles so as to indicate the cutportion.

[0167]FIG. 19 shows an IPS mode pixel pattern which has 4 maintransmitting portions in the direction which traverses the drain linesDL in the same manner as the embodiment 2. Although the constitution ofthis embodiment is similar to the constitution of the embodiment 2, theimportant feature of this embodiment lies in that a lower electrode ofthe holding capacitance Cstg is constituted of a polysilicon PSI and thepolysilicon PSI is connected to a vertical common electrode line CLMD byway of a fifth contact hole CNT5. Due to such a constitution, ashort-circuiting defect ratio on an insulating film which constitutesthe holding capacitance Cstg is reduced and hence, it is possible toprovide the liquid crystal display device which can further enhance theyield factor.

[0168] The holding capacitance Cstg is formed in the following manner.First of all, the low-temperature polysilicon PSI of the thin filmtransistor is processed in an island shape. The low-temperaturepolysilicon PSI is connected to a vertical common electrode line CLMDvia the fifth contact hole CNT5. On the other hand, a metal pixelelectrode SPM which extends from a second contact hole CNT2 of the TFTformed of low-temperature silicon PSI extends over the low-temperaturepolysilicon PSI which constitutes the lower electrode of the holdingcapacitance Cstg. The holding capacitance is formed of overlapped areaportions of the metal pixel electrode SPM and the low-temperaturepolysilicon PSI constituting the lower electrode of the holdingcapacitance Cstg which overlap each other by way of a gate insulatingfilm and an interlayer insulating film. The transparent pixel electrodeSPT is connected to the metal pixel electrode SPM via a third contacthole CNT3 and hence, a pixel potential is supplied to the liquidcrystal. On the other hand, although a transparent common electrode lineCLT is not connected to the vertical common electrode line CLMD withinthe screen, the transparent common electrode lines CLT are connected toeach other outside the screen region so as to supply the commonpotential to the liquid crystal.

[0169]FIG. 20 is a cross-sectional view taken along a cut line 20-20′ inFIG. 19. The drain voltage which constitutes the video signal istransmitted to the low-temperature polysilicon PSI from the drain lineDL via the first contact hole CNT1. When the ON voltage is applied tothe gate line GL, the MOS type TFT is operated and the video voltage istransmitted to the metal pixel electrode SPM which is connected tolow-temperature polysilicon PSI via the second contact hole CNT2.Finally, the video voltage is transmitted to the transparent pixelelectrode SPT which is connected to the metal pixel electrode SPM viathe third contact hole CNT3 and forms the pixel potential whichconstitutes one potential of the liquid crystal capacitance. The commonvoltage which constitutes another potential for driving the liquidcrystal is applied to the transparent common electrode line CLT. A newopening portion indicated by LR in FIG. 19 constitutes a newtransmitting region which is formed by the lateral electric fieldapplied to the transparent pixel electrode SPT and the transparentcommon electrode line CLT so that it is possible to provide the brightliquid crystal display device.

[0170] The lower electrode of the holding capacitance Cstg isconstituted of the low-temperature polysilicon PSI(n⁺) and theinsulating film thereof is formed of a laminated film consisting of agate insulating film GI and an interlayer insulating film ILI and hence,the insulation withstand voltage of the insulating film is higher thanthat of a single-layered film formed of the interlayer insulating filmILI of the holding capacitance of the embodiment 3. Accordingly, it ispossible to provide the IPS type liquid crystal display device which hasfewer point defects caused by the short-circuiting.

[0171] (Embodiment 4)

[0172]FIG. 21 is a plan view showing a pixel in the fourth embodimentand FIG. 22 and FIG. 23 are cross-sectional structural views taken alonga line 21-21′ and a line 22-22′ taken in the plan view of FIG. 21.

[0173] The planar pattern of the pixel shown in FIG. 21 provides theconstitution to enhance the numerical aperture with respect to a liquidcrystal television set having a large one pixel size and a large screensize. The pixel shown in FIG. 21 has 10 transmitting regions in thelateral direction and respective sizes of distances between respectivecomb-teeth electrodes which are divided into 10 are indicated by L1, L2,L3, L4, L5, L6, L7, L8, L9, L10. The interval L between respectivecomb-teeth electrodes is substantially equal to that of the embodiment 1shown in FIG. 1. This embodiment relates to the pixel pattern of the IPSliquid crystal display device which is suitable for a high-luminancetype liquid crystal television set having a large screen. In a TFT usinga low-temperature polysilicon PSI, as shown in FIG. 3, a backlight isarranged at a TFT glass substrate side and light of the backlight isdirectly irradiated to the low-temperature polysilicon PSI. Accordingly,there arises a drawback that a light irradiation leak current isincreased and hence, a pixel potential is lowered. To cope with thisdrawback, it is necessary to increase the holding capacitance of onepixel and to reduce the wiring delay of common electrode lines which maybe increased along with the increase of the holding capacitance.

[0174] With respect to the pixel shown in FIG. 21, in one pixel regionwhich is surrounded by the neighboring drain lines DL and theneighboring gate lines GL, a vertical common electrode line CLMD whichis formed by the same step and is formed of the same material as thedrain lines DL is arranged below a transparent common electrode line CLTsubstantially parallel to the drain lines DL. Since a common potentialis applied to the vertical common electrode line CLMD, with respect tothe cross-sectional structure thereof, as shown in FIG. 22, it isnecessary to arrange the vertical common electrode line CLMD below thetransparent common electrode line CLT. This is because that when thevertical common electrode line CLMD is arranged below the transparentpixel electrode SPT, the video data defined by the pixel electrode SPTand the transparent common electrode line CLT is disturbed. Accordingly,it is necessary to arrange the vertical common electrode line CLMD inplane at the inside of the first transparent pixel electrode SPT countedfrom the drain line DL by at least one comb-tooth distance (L9 in FIG.21). Further, the vertical common electrode line CLMD and the drainlines DL are formed by the same step and are formed of the same materialin the manufacturing process and hence, they are liable to be easilyshort-circuited due to dust generated in the manufacturing step and thelines become defective when the short-circuiting occurs. From thisviewpoint, it is advantageous to arrange the vertical common electrodeline CLMD toward the inner side of the pixel from the drain line DL byway of two opening portions (L9, L10 in FIG. 21) in view of enhancingthe yield factor.

[0175] The vertical common electrode line CLMD is connected to thelateral common electrode line CLMG via the fourth contact hole thusforming a metal matrix wiring on the screen and hence, even when thelarge holding capacitance is formed, it is possible to realize thescreen display which exhibits the small wiring delay and the uniformdisplay. In the plan view shown in FIG. 21, the holding capacitance is acapacitance which uses the metal pixel electrode SPM connected to theTFT portion formed of the low-temperature polysilicon PSI via the secondcontact hole CNT2 as the upper electrode and the lateral commonelectrode line CLMG as the lower electrode. Since the metal pixelelectrode SPM and the vertical common electrode line CLMD are formed bythe same step and are formed of the same material, they cannot crosseach other. Accordingly, to obtain the holding capacitance of largervalue, in the plan view of FIG. 21 and the cross-sectional view of FIG.22, it is necessary to arrange the metal pixel electrode SPM below thecomb-teeth transparent pixel electrode SPT close to the left-side drainline DL and to arrange the vertical common electrode line CLMD below thecomb-teeth transparent common electrode line CLT close to the right-sidedrain line DL. Then, by arranging at least one or more transparentcommon electrode CLT or the transparent pixel electrode SPT between themetal pixel electrode SPT and the vertical common electrode line CLMD,it is possible to set the holding capacitance to a further larger valuewhereby it is possible to provide the IPS type liquid crystal displaydevice which can be used in the application which requires the highluminance such as the liquid crystal television set. That is, it ispossible to provide the IPS type liquid crystal display device whichexhibits the high backlight luminance and also exhibits the leastluminance irregularities, the least smear, the least image retention andthe least flickers in applications which require the holding capacitanceof a large value.

[0176] The above-mentioned arrangement can be realized (1) by separatingthe transmitting region of one pixel into 6 or more transmittingregions, (2) by arranging the metal pixel electrode SPM below thecomb-teeth transparent pixel electrode SPT which is disposed closest toone drain line DL, (3) by arranging the vertical common electrode lineCLMD at the other drain line DL side and below the transparent commonelectrode CLT different from a position above the drain line DL, and (4)by arranging at least one or more transparent common electrode CLT orthe transparent pixel electrode SPT between the metal pixel electrodeSPT and the vertical common electrode line CLMD. In this embodiment, asshown in FIG. 21 and FIG. 22, 10 transmitting regions are provided and 6comb-teeth transparent electrodes are formed between the metal pixelelectrode SPM and the vertical common electrode CLMD.

[0177]FIG. 23 is a cross sectional view taken along the lateral commonelectrode line CLMG and shows the cross-sectional structure of theholding capacitance. The holding capacitance is formed by using themetal pixel electrode SPM connected to the TFT formed of thelow-temperature polysilicon PSI as an upper electrode, by using thelateral common electrode line CLMG as a lower electrode, and by usingthe interlayer insulating film ILI as the insulting film. The lateralcommon electrode line CLMG is connected to the vertical common electrodeline CLMD below the protective film PAS via a fourth contact hole CNT4so that the wiring delay time is reduced. Further, the potential of themetal pixel electrode SPM is transmitted to the transparent pixelelectrode SPT over the organic protective film FPAS so as to drive theliquid crystal. As mentioned previously, the vertical common electrodeline CLMD is arranged on the same layer as the metal pixel electrode SPMand hence, the vertical common electrode line CLMD is arranged at aposition close to the right-side drain line DL whereby it is possible toincrease the area of the metal pixel electrode SPM over the lateralcommon electrode line CLMG, that is, the holding capacitance.

[0178] (Embodiment 5)

[0179]FIG. 24 is a plan view showing a pixel in the fifth embodiment ofthe present invention and FIG. 25 is a cross-sectional view taken alonga line 25-25′ taken in FIG. 24.

[0180] The planar pattern of the pixel shown in FIG. 24 is suitable fora liquid crystal television set having a large one pixel size and alarge screen size. FIG. 24 has 10 transmitting regions and respectivesizes of distances between respective comb-teeth electrodes which aredivided into 10 are indicated by L1, L2, L3, L4, L5, L6, L7, L8, L9,L10. The interval L between respective comb-teeth electrodes issubstantially equal to that of the embodiment 1 shown in FIG. 21. Thisembodiment, in the same manner as the embodiment 4, relates to the pixelpattern of the IPS liquid crystal display device which is suitable for ahigh-luminance type liquid crystal television set having a large screen.This pattern is also a pixel method in which when a circuit using thelow-temperature silicon PSI is arranged on the TFT glass substrate GLS1,it is possible to make the maximum use of the driving ability of thecircuit.

[0181] In the same manner as the case shown in FIG. 13 of the embodiment1, the drain lines DL in the pixel region are connected to an externalcircuit IDC by way of a signal-side built-in circuit DDC on the TFTglass substrate GLS1. In the embodiment 1, three drain lines DL areconnected to the outside by way of one drain terminal Td. Accordingly,compared to the liquid crystal display device adopting the amorphoussilicon TFTs which does not incorporate the signal-side built-in circuitDDC on a glass substrate, the liquid crystal display device of thisembodiment can reduce the number of drivers used in the external circuitIDC to one third and hence, the manufacturing cost can be reduced. Onthe other hand, in this case, since the drain lines DL have to write thevideo voltage spending time three times larger than time necessary forthe liquid crystal display device adopting the amorphous silicon TFTs.Accordingly, it is necessary to reduce the wiring resistance and thecapacitance of the drain lines DL.

[0182] As shown in FIG. 21 of the embodiment 4, the lateral commonelectrode line CLMG crosses the drain line DL by way of the insulatingfilm and the parasitic capacitance of the drain line is formed at thecrossing region. Accordingly, if the crossing region can be eliminated,the parasitic capacitance of the drain line can be reduced so that thedelay time of the drain line can be reduced.

[0183]FIG. 24 is a plan view of one pixel which is provided for copingwith the above-mentioned object. Between two drain lines DL which extendin the vertical direction, 10 transmitting regions (the distances beingindicated by L1, L2, . . . L10) are provided. In the same manner as theembodiment 4, the metal pixel electrode SPM is arranged close to theleft-side drain line DL where the TFT formed of the low-temperaturepolysilicon PSI is arranged. Further, the metal pixel electrode SPM isarranged below the transparent pixel electrode SPT which is sandwichedbetween the transmitting regions L1, L2. On the other hand, the verticalcommon electrode line CLMD is not formed over the right-side drain lineDL but is arranged below the transparent common electrode CLT whichconstitutes the transparent common electrode CLT which is closest to thedrain line DL and is sandwiched between the transmitting regions L8 andL9. Due to such an arrangement, in the IPS type liquid crystal displaydevice having the pixel which has 6 or more divided transmittingregions, the holding capacitance can be maximized.

[0184] The holding capacitance has the following constitution as aplaner pattern. That is, the holding capacitance electrode STM is formedusing the same step and the same material as the gate lines GL. Theholding capacitance electrode STM is not arranged to cross the drainline DL and hence, the delay time of the drain line can be reduced. Theholding capacitance electrode STM constitute one electrode of theholding capacitance and is connected to the vertical common electrodeline CLMD via the fourth contact hole CNT4 so that the common potentialis applied to the holding capacitance electrode STM. The other electrodeof the holding capacitance is, in the same manner as the embodiment 4,constituted of the metal pixel electrode SPM which extends from thesecond contact hole CNT2 of the low-temperature polysilicon PSI. Due tosuch a constitution, the crossing area portions of the holdingcapacitance electrode STM and the metal pixel electrode SPM constitutethe holding capacitance.

[0185] In the pixel having the above-mentioned constitution, except forthe gate lines GL, the holding capacitance lines which cross the drainlines DL are eliminated and hence, the drain line capacitance is reducedwhereby the signal-side circuit on the TFT glass substrate GLS1 whichdrives the drain lines perform the favorable operation.

[0186] Further, as mentioned above, compared to the embodiment 4, theportions where the lateral common electrode line CLMG is eliminated(transmitting regions determined by distances LL, LR in the plan view ofFIG. 24) form new transmitting regions so that it is possible to providethe brighter IPS type liquid crystal display device.

[0187]FIG. 25 shows the cross-sectional structure of the pixel. That is,FIG. 25 is a cross-sectional view showing the cross section traversingthe neighboring drain lines DL and the holding capacitance electrodeSTM. The holding capacitance electrode STM which is formed by the samestep and is formed of the same material as the gate line GL is arrangedon the gate insulating film GI between the drain lines DL. The holdingcapacitance electrode STM is not extended below the drain line DL andhence, the capacitance is not formed. On the other hand, the verticalcommon electrode line CLMD which is formed by the same step and isformed of the same material as the drain line DL which is arranged overthe interlayer insulating film ILI supplies the common potential to theholding capacitance electrode STM via the fourth contact hole CNT4formed in the interlayer insulating film ILI. On the other hand, thepixel potential is supplied to the metal pixel electrode SPM from theTFT and, thereafter, the pixel potential is supplied to the transparentpixel electrode SPT via the third contact hole CNT3 formed in theorganic protective film FPAS. The holding capacitance Cstg is formedusing the above-mentioned metal pixel electrode SPM as the upperelectrode, the interlayer insulating film ILI as the insulating film andthe holding capacitance electrode STM as the lower electrode.

[0188]FIG. 25 shows the cross-sectional structure of new transmittingregions shown in the plan view of the pixel in FIG. 24. A drivingvoltage of the liquid crystal is supplied from the above-mentionedtransparent pixel electrode SPT and the transparent common electrodeCLT. The transparent common electrode CLT is not connected with thevertical common electrode line CLMD within the pixel as shown in FIG.24. The transparent common electrode CLT is arranged over the organicprotective film FPAS such that the transparent common electrode CLT alsofunctions as a black matrix BM for the gate line GL. Further, thetransparent common electrode CLT is arranged to cover the drain line DLso that the transparent common electrode CLT is arranged in a meshpattern over the whole area of the pixel region. With respect to thesupply of electricity to the transparent common electrode CLT, in thesame manner as the transparent common electrode CLT shown in FIG. 13 ofthe embodiment 1, the transparent common electrode CLT is eventuallyconnected to the common electrode bus line CLB outside the screen regionon the TFT substrate GLS1 and the common potential is supplied to thetransparent, common electrode CLT from the external power supply circuitSCC. Due to the above-mentioned two transparent electrodes, the drivingvoltage of the liquid crystal is applied to the new transmitting regionshaving gaps LL, LR between the drain lines DL and the holdingcapacitance electrode STM so that it is possible to provide the brightIPS type liquid crystal display device.

[0189] (Embodiment 6)

[0190]FIG. 26 is a plan view showing one pixel in the sixth embodimentof the present invention and FIG. 27 and FIG. 28 show thecross-sectional structures taken along a line 27-27′ and a line 28-28′of FIG. 26.

[0191] The planar pattern of the pixel shown in FIG. 26 corresponds to aliquid crystal display television set having a large one pixel size anda large screen size. The pixel shown in FIG. 26 has 10 transmittingregions and respective sizes of distances between respective comb-teethelectrodes which are divided into ten are indicated by L1, L2, L3, L4,L5, L6, L7, L8, L9, L10. The interval L between respective comb-teethelectrodes is substantially equal to that of the embodiment 4 shown inFIG. 21. Although this embodiment relates to the pixel pattern of theIPS liquid crystal display device which is suitable for a high-luminancetype liquid crystal television set having a large screen in the samemanner as the embodiment 4, this embodiment realizes the liquid crystaldisplay device which can reduce the occurrence of line defects and pointdefects on the screen.

[0192]FIG. 26 shows the pixel planar pattern which can reduce the linedefects and the point defects which occur due to short circuitingbetween comb-teeth electrodes or electrode lines made of metal which areformed by the same step and are formed of the same material as the drainlines DL. In one pixel region which is sandwiched between theneighboring gate lines GL and between the neighboring drain lines DL,the metal pixel electrode SPM and the vertical common electrode lineCLMD are formed by the same step and are formed of the same material asthe drain lines DL. Here, the metal pixel electrode SPM extends from thesecond contact hole CNT2 of the TFT formed of the low-temperaturepolysilicon PSI to the lateral common electrode line CLMG and suppliesthe pixel potential to the transparent pixel electrode SPT via the thirdcontact hole CNT3, and the vertical common electrode line CLMD extendsin the vertical direction substantially parallel to the drain lines DLand is connected to the lateral common electrode line CLMG via thefourth contact hole CLMD so as to supply the common potential to thelateral common electrode line CLMG.

[0193] In the above-mentioned constitution, when the metal pixelelectrode SPM is short-circuited with left-side drain line DL, a pointdefect occurs and when the vertical common electrode line CLMD isshort-circuited with the drain line DL, a line defect occurs. Further,when the metal pixel electrode SPM and the vertical common electrodeline CLMD are short-circuited with each other, a point defect occurs.

[0194] To reduce the short-circuiting defects which occur with a certainprobability due to a foreign substance such as a minute dust or the likeduring the manufacturing process, it is necessary to shorten the lengthof the metal electrode or the line which faces in an opposed manner onthe same plane or to elongate the distance between the electrodes whichface in the opposed manner. When the distance between the electrodeswhich face in an opposed manner is short, the length of the metalelectrodes or the lines which face in an opposed manner may beshortened.

[0195] In the pixel planar structure shown in FIG. 26, distances betweenthe vertical common electrode line CLMD and the right-side drain line DLare formed by four transmitting regions L7, L8, L9, L10 and threetransparent electrodes so that the probability of short-circuiting isreduced. On the other hands, the distances between the left-side drainline DL and the metal pixel electrode SPM are formed by threetransmitting regions L1, L2, L3 and two transparent electrodes. Further,the distances between the metal pixel electrode SPM and the verticalcommon electrode line CLMD are formed by three transmitting regions L4,L5, L6 and two transparent electrodes. In this manner, the distancesdefined among the metal pixel electrode SPM, vertical common electrodeline CLMD and drain lines DL sandwiched between the neighboring drainlines DL are arranged substantially equal with respect to the number ofdivision of the pixel. Since the number of transmitting regions inrespective distances is set to 4, 3, 3, the distances of thetransmitting regions are not completely equal. However, when the sum ofthe transmitting regions is 10, it is safe to say that the distances aresubstantially equal with respect to the number of division. This isbecause that the number of division which is close to the completelyuniform division next to the above-mentioned number of division of 4, 3,3 is the number of division of 4, 4, 2 or 5, 3, 2. In both cases, thedifference in number of transmitting regions amounts to two or more sothat the difference of the number of division in respective distances islarge compared to the case where the number of division is 4, 3, 3 withthe difference of 1.

[0196] Further, when the transmitting regions are arranged withsubstantially equal distances with respect to the number of division ofthe pixel among the metal pixel electrode SPM, the vertical commonelectrode CLMD and the drain line DL between the neighboring drain linesDL, it is necessary that at least two transparent electrodes and threetransmitting regions are arranged between the metal pixel electrode SPMand the neighboring drain line DL as well as between the metal pixelelectrode SPM and the vertical common electrode line CLMD. For this end,it is necessary to set the number of division of the pixel to 8 or more.Accordingly, when the number of division of the pixel is 8, thedistances can be divided to 3, 3, 2 so that the distances can be equallyarranged with the difference of 1. Further, when the number of divisionof pixel is 12, by dividing the pixel with the number of division of 3,5, 4, it is possible to substantially equally arrange the distances inthe arrangement adopting 12 division. This is because that when thepixel is divided with the number of division of 4, 4, 4, the transparentpixel electrode SPT cannot be arranged below the metal pixel electrodeSPM or when the pixel is divided with the number of division of 5, 5, 2,the difference is enlarged and hence, the division of 3, 5, 4 providesthe equal values. In this manner, by realizing the substantially equalarrangement within the possible arrangement, the yield factor can bemaximized. The advantageous effect on the enhancement of the yieldfactor due to the above-mentioned arrangement is not limited to the caseof the above-mentioned drain lines, the metal pixel electrode and thevertical common electrode. Similar advantageous effects can be obtainedby applying such an arrangement to any constitution of electrodes whichare formed on the same layer in a spaced-apart manner.

[0197] For example, in the pixel constitution having 8 or more dividedtransmitting regions in which the metal vertical common line CLMD isprovided between the neighboring drain line DL and the pixel potentialis supplied to the metal pixel electrode SPM from the TFT, a pixelpattern which has two comb-teeth transparent electrodes between themetal electrodes and three transmitting regions between the metalelectrodes can provide the IPS type liquid, crystal display device whichcan minimize the occurrence of short circuiting defects between themetal electrodes. Although the distance between the metal pixelelectrode SPM and the vertical common electrode CLMD and the distancebetween the metal pixel electrode SPM and the left-side drain line DLover the lateral common electrode line CLMG pattern are narrow, thelength of the electrodes or lines which face in an opposed manner is ashort value which does not extend over the pixel region and hence, theprobability of short-circuiting in these portions is small.

[0198]FIG. 27 is a cross-sectional view between the neighboring drainlines. Over the interlayer insulating film ILI formed over the TFT glasssubstrate GLS1, the metal pixel electrode SPM and the vertical commonelectrode line CLMD are arranged between the drain lines DL. The drainlines DL, the metal pixel electrode SPM and the vertical commonelectrode line CLMD are arranged substantially with equal distances thusrealizing the above-mentioned arrangement which makes the occurrence ofthe short-circuiting defects difficult. At least two or moretransmitting regions are formed between respective electrodes or lines.Further, the metal pixel electrode SPM is covered with the transparentpixel electrode SPT by way of the organic protective film FPAS and avoltage which is equal to the voltage applied to the metal pixelelectrode SPM is applied to the transparent pixel electrode SPT. Thevertical common electrode line CLMD is covered with the transparentcommon electrode CLT by way of the organic protective film FPAS and avoltage which is equal to the voltage applied to the vertical commonvoltage line CLMD is applied to the transparent common electrode CLT.Due to such a constitution, it is possible to apply an electric field Eto the liquid crystal without an error based on the applying voltagefrom respective comb-teeth transparent electrodes on the organicprotective film FPAS.

[0199]FIG. 28 is a cross-sectional view taken along the lateral commonelectrode line CLMG. Over the TFT substrate GLS1, the lateral commonelectrode line CLMG which is formed by the same step as the gate linesGL is formed. The lateral common electrode line CLMG is connected to thevertical common electrode line CLMD via the fourth contact hole CNT4formed in the interlayer insulating film ILI which covers the lateralcommon electrode line CLMG thus realizing the reduction of resistance.On the other hand, the metal pixel electrode SPM is connected to thetransparent pixel electrode SPT via the third contact hole CNT3 formedin the organic protective film FPAS which is formed over the metal pixelelectrode SPM. The organic protective film FPAS which covers the drainline DL is covered with the transparent common electrode CLT thusrealizing the arrangement which prevents an erroneous operation causedby applying an undesired electric field of the drain line DL to theliquid crystal. The holding capacitance Cstg is constituted by using thelateral common electrode line CLMG as the lower electrode, the metalpixel electrode SPM as the upper electrode and the interlayer insulatingfilm ILI as the insulating film.

[0200] (Embodiment 7)

[0201]FIG. 29 shows an example in which a liquid crystal television setis constituted by mounting the liquid crystal display device to whichany one of the embodiment 1 to embodiment 6 is applied thereon. Theliquid crystal display device LCM arranged along with speakers SP thusrealizing outputting of both of images and sound. Due to such aconstitution, a display with a clear screen which exhibits thewide-viewing angle, the high luminance and the high contrast can berealized. Further, it is also possible to realize the display with thescreen having the highly uniform luminance. Further, since theproductivity is high and the yield factor is also high, it is possibleto, provide the liquid crystal TV set at a low price.

[0202] (Embodiment 8)

[0203]FIG. 30 shows an example in which a liquid crystal monitor isconstituted by mounting the liquid crystal display device to which anyone of the embodiment 1 to embodiment 6 is applied thereon. The liquidcrystal display device LCM displays information transmitted from apersonal computer or the like thus realizing a monitor of low powerconsumption and high luminance. Due to such a constitution, a displaywith a clear screen which exhibits the wide-viewing angle, the highluminance and the high contrast can be realized. Further, it is alsopossible to realize the display with the screen having the highlyuniform luminance. Further, since the productivity is high and the yieldfactor is also high, it is possible to provide the liquid crystalmonitor at a low price.

[0204] (Embodiment 9)

[0205]FIG. 31 shows an example in which an integral type personalcomputer is constituted by mounting the liquid crystal display device towhich any one of the embodiment 1 to embodiment 6 is applied thereon.The drawing shows a notebook type personal computer PC as an example ofthe integral type personal computer and a keyboard KB is also integrallyconstituted. It is needless to say that the integral type personalcomputer is not limited to such a personal computer and includes anyliquid crystal personal computer which incorporates a liquid crystalpart and an arithmetic operation part in the same casing. The liquidcrystal display device LCM displays information transmitted from apersonal computer or the like thus realizing a display of low powerconsumption and high luminance. Due to such a constitution, a displaywith a clear screen which exhibits the wide-viewing angle, the highluminance and the high contrast can be realized. Further, it is alsopossible to realize the display with the screen having the highlyuniform luminance. Further, since the productivity is high and the yieldfactor is also high, it is possible to provide the integral typepersonal computer at a low price.

[0206] (Embodiment 10)

[0207] The embodiment realizes the stable display and the enhancement ofthe yield with the increase of the holding capacitance in a verticalelectric field method, that is, in a TN method, a VA method, a PVAmethod, a MVA method, an OCB method, or an ASV method or the like withthe use of the technical concept disclosed in any one of the embodiments1 to 9. Here, all of the TN method, the VA method, the PVA method, theMVA method, the OCB method and the ASV method per se are known and thedifference lies in the application of the technical concept disclosed inthe embodiments of the present application to these methods.

[0208] The advantageous effects of the above-mentioned embodiments arenot always limited to the lateral electric field type and even when thepresent invention is applied to the above-mentioned respective verticalelectric field methods, it is possible to achieve the partial or thewhole advantageous effects. In this case, the common electrode linesfunction as the holding capacitance lines and the common electrodes areformed on the CF substrate which faces the TFT substrate in place of thepixel electrodes on the TFT substrate.

[0209] The technical concepts disclosed in respective embodiments of thepresent application are within the range of disclosure of thespecification of the present application provided that they are withinthe scope of the technical concepts.

[0210] As has been described heretofore in detail, according to the IPSdisplay type liquid crystal display device of the present inventionwhich is mainly constituted of low-temperature polysilicon TFTs, it ispossible to provide the liquid crystal display device of high imagequality and high reliability which exhibits the high luminance, the highstability to an environment, the high productivity, the high yieldfactor, the excellent luminance uniformity, the high contrast ratio, andthe clear distinction between images.

What is claimed is:
 1. A liquid crystal display device comprising: aliquid crystal layer and a color filter layer sandwiched between a firsttransparent substrate and a second transparent substrate; a plurality ofgate lines, a plurality of drain lines which cross the plurality of gatelines in a matrix array and thin film transistors formed correspondingto respective crossing points of the gate lines and the drain lines onthe first substrate; pixel regions each of which is surrounded by theneighboring gate lines and the neighboring drain lines; each pixelincludes at least a common electrode line, a common electrode and apixel electrode; wherein the common electrode line comprising a firstcommon electrode line which extends in the extending direction of thegate lines and a second common electrode line which extends in theextending direction of the drain lines in the pixel region, the firstcommon electrode line and the second common electrode line are spacedapart from each other by way of a first insulating film, the firstcommon electrode line and the second common electrode line are connectedvia an opening portion formed in the first insulating film, and a secondinsulating film is formed over the opening portion.
 2. A liquid crystaldisplay device according to claim 1, wherein the first common electrodeline and the second common electrode line include at least the secondinsulating film between the common electrode in the pixel region, andthe common electrode includes a portion which is arranged over the drainline by way of at least the second insulating film such that the portionhas a width larger than a width of the drain line.
 3. A liquid crystaldisplay device comprising: a liquid crystal layer and a color filterlayer sandwiched between a first transparent substrate and a secondtransparent substrate; a plurality of gate lines, a plurality of drainlines which cross the plurality of gate lines in a matrix array and thinfilm transistors formed corresponding to respective crossing points ofthe gate lines and the drain lines on the first substrate; pixel regionseach of which is surrounded by the neighboring gate lines and theneighboring drain lines, each pixel includes at least a common electrodeline and a pixel electrode, wherein the liquid crystal display devicecomprising a first island-like electrode in the pixel region, includesan opening portion formed in a first insulating film which covers thefirst island-like electrode, includes a common electrode line whichextends in the extending direction of the drain lines, wherein the firstisland-like electrode and the common electrode line are connected viathe opening portion, the first is land-like electrode constitutes alower electrode, and a second island-like electrode which is connectedto a source of the thin film transistor and is formed on the firstinsulating film constitutes an upper electrode thus forming holdingcapacitance.
 4. A liquid crystal display device according to claim 3,wherein the liquid crystal display device includes the common electrodeswhich are constituted over an insulating film which covers the drainline over the first substrate, the common electrodes are connected in amatrix array between neighboring pixels, and the common electrodesinclude portions which have a width wider than a width of the drainlines over an insulating film which are applied onto the drain lines. 5.A liquid crystal display device according to claim 3, wherein theinsulating film of the holding capacitance is an inorganic insulatingfilm which covers the gate line of the thin film transistor.
 6. A liquidcrystal display device according to claim 3, wherein the firstisland-like electrode is constituted of a semiconductor layer of thethin film transistor and the insulating film of the holding capacitanceincludes at least a gate insulating film of the thin film transistor. 7.A liquid crystal display device comprising: a liquid crystal layer and acolor filter layer sandwiched between a first substrate and a secondsubstrate; a plurality of gate lines, a plurality of drain lines whichcross the plurality of gate lines in a matrix array and thin filmtransistors formed corresponding to respective crossing points of thegate lines and the drain lines on the first substrate; pixel regionseach of which is surrounded by the neighboring gate lines and theneighboring drain lines, wherein each pixel includes at least a commonelectrode line, a common electrode and a pixel electrode; wherein theliquid crystal display device comprising a common electrode line whichextends in the extending direction of the drain line as the commonelectrode line, includes an island-like metal pixel electrode which isconnected to a source of the thin film transistor, wherein the pixelregion includes an opening portion which is divided into 6 or moreopening portions between the neighboring drain lines, at least 1 dividedopening portion is arranged between the island-like metal pixelelectrode and one of the neighboring drain lines, at least 2 dividedopening portions are arranged between the common electrode line and theother of the neighboring drain lines, and at least 3 divided openingportions are arranged between the island-like metal pixel electrode andthe common electrode line.
 8. A liquid crystal display devicecomprising: a liquid crystal layer and a color filter layer sandwichedbetween a first substrate and a second substrate; a plurality of gatelines, a plurality of drain lines which cross the plurality of gatelines in a matrix array and thin film transistors formed correspondingto respective crossing points of the gate lines and the drain lines onthe first substrate; pixel regions each of which is surrounded by theneighboring gate lines and the neighboring drain lines, wherein eachpixel includes at least a common electrode line, a common electrode anda pixel electrode, wherein the liquid crystal display device comprisinga common electrode line which extends in the extending direction of thedrain line as the common electrode line, includes an island-like metalpixel electrode which is connected to a source of the thin filmtransistor, wherein the pixel region includes an opening portion whichis divided into 8 or more opening portions between the neighboring drainlines, at least 3 divided opening portions are arranged between theisland-like metal pixel electrode and one of the neighboring drainlines, at least 2 divided opening portions are arranged between thecommon electrode line and the other of the neighboring drain lines, andat least 3 divided opening portions are arranged between the island-likemetal pixel electrode and the common electrode line.
 9. A liquid crystaldisplay device comprising: a liquid crystal layer and a color filterlayer sandwiched between a first substrate and a second substrate; aplurality of gate lines, a plurality of drain lines which cross theplurality of gate lines in a matrix array and thin film transistorsformed corresponding to respective crossing points of the gate lines andthe drain lines on the first substrate; pixel regions each of which issurrounded by the neighboring gate lines and the neighboring drainlines, each pixel includes at least a common electrode line, atransparent common electrode and a transparent pixel electrode; whereinthe transparent common electrode and the transparent pixel electrode areformed on a same layer above the drain lines, the liquid crystal displaydevice includes a common electrode line which extends in the extendingdirection of the drain line as the common electrode line, a metal pixelelectrode which is connected to a source of the thin film transistor,wherein the pixel region includes an opening portion which is dividedinto 6 or more opening portions between the neighboring drain lines, themetal pixel electrode is arranged below the transparent pixel electrodewhich is arranged closest to one drain line of the neighboring drainlines, the common electrode line is arranged close to the other drainline of the neighboring drain lines and below the transparent commonelectrode which is not arranged on the other drain line, and at least 1or more transparent common electrode or 1 or more transparent pixelelectrodes are arranged between the metal pixel electrode and the commonelectrode line.
 10. A liquid crystal display device comprising: a liquidcrystal layer and a color filter layer sandwiched between a firstsubstrate and a second substrate; a plurality of gate lines, a pluralityof drain lines which cross the plurality of gate lines in a matrix arrayand thin film transistors formed corresponding to respective crossingpoints of the gate lines and the drain lines on the first substrate;pixel regions each of which is surrounded by the neighboring gate linesand the neighboring drain lines, wherein each pixel includes at least acommon electrode line, a transparent common electrode and a transparentpixel electrode; wherein the liquid crystal display device comprising ametal pixel electrode which is arranged in a region sandwiched by theneighboring drain lines, includes a common electrode which extends inthe extending direction of the drain line as the common electrode, and adistance between one of the neighboring drain lines and the metal pixelelectrode, a distance between the metal pixel electrode and the commonelectrode and a distance between the common electrode and the other ofthe neighboring drain lines are set to approximately equal with respectto the number of division of the pixel region.
 11. A liquid crystaldisplay device according to claim 7, wherein the liquid crystal displaydevice includes a first common electrode line which extends in theextending direction of the gate lines as the common electrode line and asecond common electrode line which extends in the extending direction ofthe drain line, and the first common electrode line and the secondcommon electrode line are connected to each other via an opening portionof an insulating film in the pixel region.
 12. A liquid crystal displaydevice according to claim 10, wherein the approximately equal distanceswith respect to the number of division of the pixel region are set to3+3+2 in the liquid crystal display device in which the number ofdivision of the a region between the neighboring drain signal lines is8, are set to 3+3+4 in the liquid crystal display device in which thenumber of division of the a region between the neighboring drain signallines is 10, and are set to 5+4+3 in the liquid crystal display devicein which the number of division of the a region between the neighboringdrain signal lines is
 12. 13. A liquid crystal display devicecomprising: a liquid crystal layer and a color filter layer sandwichedbetween a first transparent substrate and a second transparentsubstrate; a plurality of gate lines, a plurality of drain lines whichcross the plurality of gate lines in a matrix array and thin filmtransistors formed corresponding to respective crossing points of thegate lines and the drain lines on the first substrate; pixel regionseach of which is surrounded by the neighboring gate lines and theneighboring drain lines, wherein each pixel includes at least a holdingcapacitance line and a pixel electrode; wherein the liquid crystaldisplay device comprising a first island-like electrode in the pixelregion, includes an opening portion formed in a first insulating filmwhich covers the first island-like electrode, includes a holdingcapacitance line which extends in the extending direction of the drainlines, wherein the first island-like electrode and the holdingcapacitance line are connected via the opening portion, the firstisland-like electrode constitutes a lower electrode, and a secondisland-like electrode which is connected to a source of the thin filmtransistor and is formed on the first insulating film constitutes anupper electrode thus forming holding capacitance.
 14. A liquid crystaldisplay device according to claim 13, wherein the liquid crystal displaydevice includes a second holding capacitance line which extends in theextending direction of the gate lines, and the second holdingcapacitance line and the holding capacitance line which extends in theextending direction of the drain lines are electrically connected via athrough hole formed in the first insulating film.
 15. A liquid crystaldisplay device according to claim 13, wherein the liquid crystal displaydevice includes a second holding capacitance line which extends in theextending direction of the gate lines and the second holding capacitanceline also functions as the first island-like electrode.
 16. A liquidcrystal display device comprising: a liquid crystal layer and a colorfilter layer sandwiched between a first transparent substrate and asecond transparent substrate; a plurality of gate lines, a plurality ofdrain lines which cross the plurality of gate lines in a matrix arrayand thin film transistors formed corresponding to respective crossingpoints of the gate lines and the drain lines on the first substrate;pixel regions each of which is surrounded by the neighboring gate linesand the neighboring drain lines, wherein each pixel includes a commonelectrode line, a transparent common electrode and a pixel electrode,wherein an insulating film is formed over the gate line, the transparentcommon electrode is formed over the insulating film and has a regionwhich covers the insulating film and has a width which is larger than awidth of the gate line, and the transparent electrode line having thewidth wider than the width of the gate line plays a role of a blackmatrix in the liquid crystal display device.
 17. A liquid crystaldisplay device according to claim 16, wherein the transparent electrodeline having the width wider than the width of the gate line also coversa semiconductor layer of the thin film transistor.
 18. A liquid crystaldisplay device according to claim 16, wherein the insulating film is anorganic insulating film made of acrylic resin or the like.
 19. A liquidcrystal display device according to claim 1, wherein the commonelectrode and the pixel electrodes are formed of a transparent electrodeand both electrodes are formed as an uppermost layer of the firstsubstrate below an orientation film.
 20. A liquid crystal display deviceaccording to claim 1, wherein the liquid crystal display device is alateral electric field type liquid crystal display device.
 21. A liquidcrystal display device according to claim 1, wherein a semiconductorlayer of the thin film transistor is formed of polysilicon.
 22. An imagedisplay device which is used as a liquid crystal television comprisingthe liquid crystal display device according to claim
 1. 23. An imagedisplay device which is used as a liquid crystal monitor comprising theliquid crystal display device according to claim
 1. 24. An image displaydevice which is used as an integral type personal computer comprisingthe liquid crystal display device according to claim 1.